[5p-A204-1~9] Science of impurity control in silicon wafers

[5p-A204-1] Recent gettering technology trends for silicon devices from device engineering perspective

〇Kensuke Okonogi¹ (1.Micron Memory Japan)

Keywords:Gettering

Depending on the requirements of portable electronic devices, current advanced memory devices have a minimum feature size of 10 nm scale. Chip stack technology such as Through Silicon Via (TSV) process has been developed to increase capacity and multifunctionality. These state-of-the-art technologies also require optimal crystallinity for silicon wafers. Based on the trend of silicon wafers for DRAM and grasping current problems from technical papers, I would like to discuss future gettering development.