The 78th JSAP Autumn Meeting, 2017

Presentation information

Symposium (Oral)

Symposium » Nanoscale 3D analyses for new device and materials development

[6p-C19-1~8] Nanoscale 3D analyses for new device and materials development

Wed. Sep 6, 2017 1:45 PM - 5:30 PM C19 (C19)

Masato Koyama(TOSHIBA), Tomihiro Hashizume(Hitachi, Ltd.)

2:45 PM - 3:15 PM

[6p-C19-3] Development of Local DLTS Based on Super-Higher-Order Scanning Nonlinear Dielectric Microscopy and Its Application to MOS Interface Characterization

Norimichi Chinone1, 〇Yasuo Cho1 (1.Tohoku Univ.)

Keywords:Local deep level transient spectroscopy

Physical properties of metal-oxide-semiconductor (MOS) interface are critical for semiconductor devices. There are several techniques for characterizing MOS interface properties. Deep level transient spectroscopy (DLTS) is one of powerful techniques capable of macroscopic quantitative evaluation of trap density at/near MOS interface (Dit). But it is easily imagined that actual trap is not homogeneously distributed but has two dimensional distributions in atomic scale and even in mesoscopic scale. Therefore, it is very important to characterize MOS interface microscopically. Unfortunately, it is impossible to observe such inhomogeneity by using conventional macroscopic DLTS method. Moreover, in our best knowledge, scanning probe microscopy based two dimensional DLTS imaging has not been reported.
In this presentation, a new technique for local DLTS imaging based on scanning nonlinear dielectric microscopy (SNDM) is proposed. This method enables us to observe two dimensional distribution of trap density at/near MOS interface and is demonstrated with oxidized SiC wafer.
45-nm-thick thermal oxide layers were formed on three Si-faces of 4°-off n-type 4H-SiC wafers. One of them was labeled as #S-45-1. The other two wafers were subjected to post-oxidation annealing (POA) in nitric oxide (NO) at different conditions as follows: 1250°C for 10 minutes (#S-45-2), 1150°C for 60 minutes (#S-45-3). The average Dit values of these samples were preliminarily measured by conventional macroscopic High-Low method, which showed that the Dit of #S-45-1 was highest and that of #S-45-3 was lowest.
These three samples were scanned on 1.5x1.5mm2 square area with a resolution of 30x30 pixels and analyzed using the proposed local DLTS method.
By analyzing the acquired images, time-constant t and magnitude of transient capacitance response were obtained at each pixel. Images of local DLTS signal shows highest brightness was obtained from #S-45-1 and lowest one was obtained from #S-45-3, which is consistent with macroscopically obtained result. Furthermore, in the local DLTS images, we detected dark and bright areas, which can be translated as two dimensional trap distribution.
Next, quantitative imaging of Dit by local-DLTS was performed. The averaged Dits in the local-DLTS images are same order of magnitude as Dit values at corresponding energy level measured by macroscopic High-Low method. All images have dark and bright areas with feature size of a few 100 nm. In addition, the images with different time constant showed different distribution, which implies that the distribution of interface traps depends on time constant, or suggests the physical origin of interface trap with different energy level is different.
Thus, we conclude that this local DLTS technique can contribute to understanding of two dimensionally distributed microscopic physical properties of MOS interface.