[6p-C21-1~20] 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

[6p-C21-14] Fabrication of Micro-SOI-Diaphragm Structures Using Minimal Deep-RIE and Mask Aligner

〇Yongxun Liu¹, Hiroyuki Tanaka¹, Norio Umeyama¹, Sommawan Khumpuang¹, Masayoshi Nagao¹, Takashi Matsukawa¹, Shiro Hara¹ (1.AIST)

Keywords:SOI, diaphragm

Recently, we have developed the SOI-CMOS integrated circuits using minimal-fab and mega-fab hybrid processes. In this work, as one of the basic MEMS structures, we fabricate PMOSFETs on SOI diaphragms by using the minimal deep-RIE and mask aligner, and investigate the elctrical characteristics of the fabricated PMOSFETs.