The 78th JSAP Autumn Meeting, 2017

Presentation information

Oral presentation

13 Semiconductors » 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

[6p-C21-1~20] 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

Wed. Sep 6, 2017 1:45 PM - 7:00 PM C21 (C21)

Kuniyuki Kakushima(Titech), Masato Sone(Titech)

5:00 PM - 5:15 PM

[6p-C21-13] MEMS Piezo-resistive Accelerometer Fabricated by Full Minimal Fab Process

AnhTuan Phan1,2, Hiroyuki Tanaka1,3, Norio Umeyama1,3, Noriko Miura1,3, Khumpuang Sommawan1,3, Shiro Hara1,3 (1.Minimal Fab, 2.SHTPLabs, 3.AIST)

Keywords:MEMS Piezo-resistive Accelerometer, Minimal Fab

In the semiconductor industry, the trend of manufacturing integrated circuits (IC) is to enlarge silicon wafer size from 300 mm to 450 mm. The transition to the next larger wafer size enables the fabrication of more chip per wafer. However, it causes a larger investment cost. The resulting increase in price will certainly push up the research and development cost of new semiconductor devices. A novel semiconductor manufacturing system called “minimal fab” has been developed for customized semiconductor devices and microelectromechanical systems (MEMS) with low costs [1]. Micro-needle structure was the first micro-structure that was successfully fabricated using the minimal fab [2]. In this work, for the first time, we develop a MEMS piezo-resistive accelerometer in which the fabrication process is fully compatible with both IC process technology and bulk micromachining technology.