The 78th JSAP Autumn Meeting, 2017

Presentation information

Oral presentation

13 Semiconductors » 13.1 Fundamental properties, surface and interface, and simulations of Si related materials

[8a-A411-1~10] 13.1 Fundamental properties, surface and interface, and simulations of Si related materials

Fri. Sep 8, 2017 9:00 AM - 11:45 AM A411 (411)

Takashi Hasunuma(Univ. of Tsukuba)

9:45 AM - 10:00 AM

[8a-A411-4] Heavy Ion Generated Current Leading to Long Line-type Soft Errors in Thin BOX SOI SRAMS

〇(D)ChinHan Chung1,2, Daisuke Kobayashi1,2, Kazuyuki Hirose1,2 (1.Univ. of Tokyo, 2.ISAS/JAXA)

Keywords:silicon on insulator, simulation, soft error

The silicon-on-insulator (SOI) CMOS technology adopting an thin buried-oxide (BOX) layer has various advantages over conventional structures, including the ability to increase device performance by changing the back-bias, as well as higher soft error tolerance.
Recently, in a heavy ion test, we have discovered a new soft error inside thin-BOX SOI SRAMs, which put its high soft error tolerance in question. Compared with the case without back-bias, which exhibited mostly SBUs, long MCUs (10 cells or more) along the bit line direction have been observed. The cross-section of the device, which represents the device sensitive region, also increased by more than 100 times when back-bias was applied. This phenomenon cannot be explained by other previous works. We aim to find the mechanism behind this phenomenon by studying the movement of the ion-generated carriers in the region under the BOX.