09:45 〜 10:00
▼ [8a-A411-4] Heavy Ion Generated Current Leading to Long Line-type Soft Errors in Thin BOX SOI SRAMS
キーワード：silicon on insulator, simulation, soft error
The silicon-on-insulator (SOI) CMOS technology adopting an thin buried-oxide (BOX) layer has various advantages over conventional structures, including the ability to increase device performance by changing the back-bias, as well as higher soft error tolerance.
Recently, in a heavy ion test, we have discovered a new soft error inside thin-BOX SOI SRAMs, which put its high soft error tolerance in question. Compared with the case without back-bias, which exhibited mostly SBUs, long MCUs (10 cells or more) along the bit line direction have been observed. The cross-section of the device, which represents the device sensitive region, also increased by more than 100 times when back-bias was applied. This phenomenon cannot be explained by other previous works. We aim to find the mechanism behind this phenomenon by studying the movement of the ion-generated carriers in the region under the BOX.
Recently, in a heavy ion test, we have discovered a new soft error inside thin-BOX SOI SRAMs, which put its high soft error tolerance in question. Compared with the case without back-bias, which exhibited mostly SBUs, long MCUs (10 cells or more) along the bit line direction have been observed. The cross-section of the device, which represents the device sensitive region, also increased by more than 100 times when back-bias was applied. This phenomenon cannot be explained by other previous works. We aim to find the mechanism behind this phenomenon by studying the movement of the ion-generated carriers in the region under the BOX.