The 64th JSAP Spring Meeting, 2017

Presentation information

Oral presentation

13 Semiconductors » 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

[16a-E206-1~13] 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

Thu. Mar 16, 2017 9:00 AM - 12:15 PM E206 (E206)

Masato Sone(Titech), Masahide Goto(NHK)

11:45 AM - 12:00 PM

[16a-E206-12] Fan-Out type RDL package fabrication using hybrid process of minimal package process and conventional metal PVD

Masanori Iwata1, Toru Mannami1, Nobuyoshi Yamauchi1, Kenji Miyake1, Fumito Imura2, Sommawan Khumpuang2, Shiro Hara2 (1.PMT, 2.AIST)

Keywords:redistribution layer, FOWLP, minimal process

In recent years, the demand from consumers for downsizing of electronic products and high integrations has been increasing. SoC (System-of-Chip) and SiP (System in Package) technologies have been developed to fulfill their requirements. SoC is an integrated circuit (IC) that integrates all components into one chip. It is possible to obtain all-full function in one chip. But there are some limitations of integrated functions into it. Furthermore, high cost is required if the SoC is made for each application. The SiP is made up of a number of integrated circuits that are enclosed in a single package. The dies are placed on the interposer and are connected with wire. And, there are some limitations for downsizing. The FOWLP (Fan-Out Wafer Level Package) with less-interposer and less-wire is one of the solutions to downsizing a SiP. The production of such FOWLP, with larger size wafers, is suitable for mass production, but is not suitable for small quantity and large variety. The minimal package will be one of solutions for small quantity and large variation production. We made an experiment to produce fan-out type RDL (Redistribution Layer) packages with the hybrid process using the minimal package process and conventional metal PVD.The structure of our experimental FOWLP is RDL/ Dielectric layer / TEG Si chip embedded in mold resin on Si substrate. The reconstituted substrate, which is a TEG Si chip (4mm x 4mm) embedded in mold resin, is 12.5mmΦ, which is half inch size.The minimal hybrid process is the minimal package process and conventional Cu/Ti sputtering process for Cu seed deposition. The minimal package process is composed of the following: die bonder, coater, maskless exposure system, developer, Cu electric plating machine, and Cu wet etcher. This minimal package process is capable of achieving shorter cycle times with a single wafer process. And it’s also possible to save cost and production time of the photomasks because of the maskless exposure system. Therefore, the minimal hybrid process will be suitable for small quantities and large variations in production. We’ll continue to develop the process technology for FOWLP production with minimal package process.