[18p-G203-1~18] 13.5 Semiconductor devices and related technologies

[18p-G203-1] Lowering data retention voltage in static random access memory array by post-fabrication self-improvement of cell stability by multiple stress application

〇Tomoko Mizutani¹, Kiyoshi Takeuchi¹, Takuya Saraya¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (1.IIS, Univ. of Tokyo)

Keywords:SRAM, self-improvement technique, data retention voltage

This paper proposes a new version post-fabrication SRAM self-improvement technique, which utilizes multiple stress applications. It is demonstrated that lowering of data retention voltage (DRV) is more effectively achieved than the previously proposed single stress technique.