The 65h JSAP Spring Meeting, 2018

Presentation information

Oral presentation

13 Semiconductors » 13.7 Compound and power electron devices and process technology

[19a-C302-1~12] 13.7 Compound and power electron devices and process technology

Mon. Mar 19, 2018 9:00 AM - 12:15 PM C302 (52-302)

Makoto Miyoshi(Nagoya Inst. of Tech.)

11:15 AM - 11:30 AM

[19a-C302-9] Characterization of traps in MOCVD p-GaN by low-frequency capacitance DLTS

〇(M1)Tatsuya Kogiso1, Yutaka Tokuda1, Tetsuo Narita2, Kazuyoshi Tomita2, Tetsu Kachi3 (1.Aichi Inst. of Technol., 2.Toyota Central R&D Labs., Inc., 3.Nagoya University)

Keywords:DLTS, p-GaN

We have studied traps in p-GaN using the p++p-n+ junction grown by MOCVD on n+-GaN substrate with capacitance (C) DLTS measurements. 1 MHz CDLTS is usually employed, but the lowest temperature is restricted to around 200 K due to the freeze-out of Mg acceptors. In this study, 1 kHz CDLTS is applied and the lowest measurement is extended to 110 K. Two hole traps labelled Ha (0.29 eV) and Hb (0.33 eV) are found with high trap concentrations.