Tomohiko Yamagishi

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Speaker, Author, Co-Author

Wed. Sep 18, 2019 9:00 AM - 12:00 PM B11 (B11)

Oral presentation
| 13 Semiconductors
| 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[18a-B11-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

9:45 AM - 10:00 AM

[18a-B11-4] NOR and NAND Cell Layout using p/n-Vertically-Integrated Nanowire FET

〇Tomohiko Yamagishi¹, Atsushi Hori¹, Iriya Muneta¹, Kuniyuki Kakushima¹, Kazuo Tsutsui¹, Hitoshi Wakabayashi¹ (1.Tokyo Tech.)