Oral presentation

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[18a-B11-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Wed. Sep 18, 2019 9:00 AM - 12:00 PM B11 (B11)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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9:00 AM - 9:15 AM

[18a-B11-1] Critical role of thermal runaway in VO₂ voltage-induced metal-insulator transition

〇Takeaki Yajima^1,2, Tomonori Nishimura¹, Takahisa Tanaka¹, Ken Uchida¹, Akira Toriumi¹ (1.Univ. of Tokyo, 2.JST PRESTO)

9:15 AM - 9:30 AM

△ [18a-B11-2] Evaluation of electrical resistance for O₂-annealed TaO_xReRAM

〇(M1C)Soshun Doko¹, Yoshiaki Ishii¹, Masahiro Moniwa¹ (1.Tokyo Univ. of Tecnology)

9:30 AM - 9:45 AM

[18a-B11-3] Driver-Transistor Scaling for Memory with Asymmetric Source/Drain Structure Suppressing Variation in Threshold Voltage

〇Kazuya Fukase¹, Minoru Oda¹, Toshitaka Miyata¹, Hiroki Okamoto¹, Akira Hokazono¹, Isamu Ito¹, Masato Koyama¹ (1.Toshiba Memory)

9:45 AM - 10:00 AM

[18a-B11-4] NOR and NAND Cell Layout using p/n-Vertically-Integrated Nanowire FET

〇Tomohiko Yamagishi¹, Atsushi Hori¹, Iriya Muneta¹, Kuniyuki Kakushima¹, Kazuo Tsutsui¹, Hitoshi Wakabayashi¹ (1.Tokyo Tech.)

10:00 AM - 10:15 AM

[18a-B11-5] Statistical Analyses of Worst Case SRAM Data Retention Voltage by Extreme Value Theory

〇Tomoko Mizutani¹, Kiyoshi Takeuchi¹, Takuya Saraya¹, Masaharu Kobayashi^1,2, Toshiro Hiramoto¹ (1.IIS, Univ. of Tokyo, 2.VDEC, Univ. of Tokyo)

10:15 AM - 10:30 AM

[18a-B11-6] A Feasibility Study on Ferroelectric Shadow SRAM Using a New Variability Design Scheme

〇KIYOSHI TAKEUCHI¹, MASAHARU KOBAYASHI¹, TOSHIRO HIRAMOTO¹ (1.IIS, Univ. Tokyo)

10:45 AM - 11:00 AM

[18a-B11-7] Design and performance of Flip-Flops configured with piezoelectronic transistors

〇Yusaku Shiotsu¹, Shuu'ichirou Yamamoto¹, Hiroshi Funakubo², Minoru Kuribayashi Kurosawa³, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst of Tech, 2.Sch. of Mater. and Chem. Tech., Tokyo Inst of Tech, 3.Sch. of Eng., Tokyo Inst of Tech)

11:00 AM - 11:15 AM

[18a-B11-8] Performance of nonvolatile power-gating using VNR-SRAM and NV-SRAM

〇Hayato Yoshida¹, Daiki Kitagata¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST,Tokyo Inst. of Tech.)

11:15 AM - 11:30 AM

[18a-B11-9] Performance evaluation of power gating architectures using nonvolatile/virtually-nonvolatile Flip-Flops

〇Kenichiro Takiguchi¹, Daiki Kitagata¹, Tsubasa Matsuzaki¹, Syuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

11:30 AM - 11:45 AM

[18a-B11-10] Power-gating performance of SRAM using various retention techniques

〇Takumi Hara¹, Hayato Yoshida¹, Daiki Kitagata¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.Tokyo Tech)

11:45 AM - 12:00 PM

[18a-B11-11] Nonvolatile power-gating using NV-SRAM based on the proactive flash of useless data

〇Daiki Kitagata¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

Session information

[18a-B11-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[18a-B11-1] Critical role of thermal runaway in VO₂ voltage-induced metal-insulator transition

△ [18a-B11-2] Evaluation of electrical resistance for O₂-annealed TaO_xReRAM

[18a-B11-3] Driver-Transistor Scaling for Memory with Asymmetric Source/Drain Structure Suppressing Variation in Threshold Voltage

[18a-B11-4] NOR and NAND Cell Layout using p/n-Vertically-Integrated Nanowire FET

[18a-B11-5] Statistical Analyses of Worst Case SRAM Data Retention Voltage by Extreme Value Theory

[18a-B11-6] A Feasibility Study on Ferroelectric Shadow SRAM Using a New Variability Design Scheme

[18a-B11-7] Design and performance of Flip-Flops configured with piezoelectronic transistors

[18a-B11-8] Performance of nonvolatile power-gating using VNR-SRAM and NV-SRAM

[18a-B11-9] Performance evaluation of power gating architectures using nonvolatile/virtually-nonvolatile Flip-Flops

[18a-B11-10] Power-gating performance of SRAM using various retention techniques

[18a-B11-11] Nonvolatile power-gating using NV-SRAM based on the proactive flash of useless data

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Session information

[18a-B11-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

△ [18a-B11-2] Evaluation of electrical resistance for O2-annealed TaOxReRAM

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△ [18a-B11-2] Evaluation of electrical resistance for O₂-annealed TaO_xReRAM