The 80th JSAP Autumn Meeting 2019

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[18a-B11-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Wed. Sep 18, 2019 9:00 AM - 12:00 PM B11 (B11)

Masumi Saitoh(Toshiba Memory)

9:15 AM - 9:30 AM

[18a-B11-2] Evaluation of electrical resistance for O2-annealed TaOxReRAM

〇(M1C)Soshun Doko1, Yoshiaki Ishii1, Masahiro Moniwa1 (1.Tokyo Univ. of Tecnology)

Keywords:wearable, non-volatile memory, ReRAM

Resistive Random Access Memory (ReRAM) attracts much attention for low power application of IoT wearable edge devices. In this study, O2-annealing process step was inserted just after oxide-layer (TaOx) deposition, and electrical resistance of the ReRAM was investigated as a function of the annealing temperature. The annealing reduces oxygen vacancy concentration in the oxide-layer and increases HRS resistance, while LRS resistance stays at the similar level. Consequently, a high resistance ratio (> 4 orders of magnitude) can be realized.