[19a-E304-1~12] 13.4 Si processing /Si based thin film / MEMS / Equipment technology

▼ [19a-E304-11] Annealing Effect on Room-Temperature-Deposited SiO₂ Liner for Multichip-to-Wafer 3D Integration Process

〇(M2C)Rui Liang¹, Sungho Lee¹, Yuki Miwa¹, Kousei Kumahara¹, Hisashi Kino³, Takafumi Fukushima², Tetsu Tanaka^1,2 (1.BME of Tohoku Univ., 2.ME of Tohoku Univ., 3.FIRS of Tohoku Univ.)

Keywords:TSV, Low temperature, 3DIC

3D-ICs have many advantages, such as short interconnect length, high-speed operation, and parallel processing[1]. Compared with wafer-to-wafer (WtW) and chip-to-chip (CtC) 3D integration processes,multichip-to-wafer (MCtW) 3D integration allows for higher production yield, higher throughput, and more chip-size flexibility in stacking.
In typical 3DIC, through-Si vias (TSVs) and metal mircobumple are accepted as vertical interconnect asscess to stack chips. TSV dielectric liner, SiO₂layer, requires high temperature in the conventional deposition process to improve the quality of the TSV liner. The high temperature during the MC2W process based on a via-last TSV approach will cause chip/wafer warpage and delamination due to the viscoelasticity change of the temporary adhesive between chips and a supporting substrate.
Recently, a new kind CVD, called OER (Ozone-Ethylene Radical generation)-TEOS-CVD, has developed to deposit SiO₂by mixing pure O₃and ethylene at low temperatures. We have applied this new method to the TSV formation [2]. In this study, we evaluate the effect of the annealing on the SiO₂deposited by OER-TEOS-CVD using a TSV-structured metal-insulator-semiconductor (MIS) capacitors to obtain high-quality TSV liners.