11:30 〜 11:45
▼ [19a-E304-11] Annealing Effect on Room-Temperature-Deposited SiO2 Liner for Multichip-to-Wafer 3D Integration Process
キーワード：TSV, Low temperature, 3DIC
3D-ICs have many advantages, such as short interconnect length, high-speed operation, and parallel processing[1]. Compared with wafer-to-wafer (WtW) and chip-to-chip (CtC) 3D integration processes,multichip-to-wafer (MCtW) 3D integration allows for higher production yield, higher throughput, and more chip-size flexibility in stacking.
In typical 3DIC, through-Si vias (TSVs) and metal mircobumple are accepted as vertical interconnect asscess to stack chips. TSV dielectric liner, SiO2layer, requires high temperature in the conventional deposition process to improve the quality of the TSV liner. The high temperature during the MC2W process based on a via-last TSV approach will cause chip/wafer warpage and delamination due to the viscoelasticity change of the temporary adhesive between chips and a supporting substrate.
Recently, a new kind CVD, called OER (Ozone-Ethylene Radical generation)-TEOS-CVD, has developed to deposit SiO2by mixing pure O3and ethylene at low temperatures. We have applied this new method to the TSV formation [2]. In this study, we evaluate the effect of the annealing on the SiO2deposited by OER-TEOS-CVD using a TSV-structured metal-insulator-semiconductor (MIS) capacitors to obtain high-quality TSV liners.
In typical 3DIC, through-Si vias (TSVs) and metal mircobumple are accepted as vertical interconnect asscess to stack chips. TSV dielectric liner, SiO2layer, requires high temperature in the conventional deposition process to improve the quality of the TSV liner. The high temperature during the MC2W process based on a via-last TSV approach will cause chip/wafer warpage and delamination due to the viscoelasticity change of the temporary adhesive between chips and a supporting substrate.
Recently, a new kind CVD, called OER (Ozone-Ethylene Radical generation)-TEOS-CVD, has developed to deposit SiO2by mixing pure O3and ethylene at low temperatures. We have applied this new method to the TSV formation [2]. In this study, we evaluate the effect of the annealing on the SiO2deposited by OER-TEOS-CVD using a TSV-structured metal-insulator-semiconductor (MIS) capacitors to obtain high-quality TSV liners.