The 80th JSAP Autumn Meeting 2019

Presentation information

Poster presentation

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[19p-PB2-1~7] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Thu. Sep 19, 2019 1:30 PM - 3:30 PM PB2 (PB)

1:30 PM - 3:30 PM

[19p-PB2-1] Performance enhancement of extremely thin body SiGe or Ge on insulator pMOSFETs fabricated by Ge condensation

〇(DC)KwangWon Jo1, Takagi Shinichi1, Mitsuru Takenaka1 (1.The Univ. of Tokyo)

Keywords:Ge-on-Insulator, Strain, Ge condensation

Ultrathin GOI and SGOI MOSFETs have attracted much attention as p-channel devices, because of the high hole mobility (μh) with suppression of short channel effects. Here, strain engineering also plays a key factor to enhance the performance of pMOSFET. On the other hand, compressive strain (εc) can be easily relaxed in high Ge fractions because of various crystal defects induced during the Ge condensation . We have succeeded in suppression of strain relaxation thorough an improved condensation method, composed of slow-cooling and a thinned initial SiGe layer in the previous report [2]. By employing this method, μh of 467 cm2/Vs was obtained for 10 nm-thick GOI pMOSFETs with εc of ~1.75 % . In this work, thinning of GOI and SGOI films fabricated by this condensation process is conducted down to 2 nm and compressively-strained 2- nm-thick ETB GOI and SGOI pMOSFETs are shown to operate with higher μh than the reported ones. Also, the impact of the ETB thickness on the electrical characteristics is quantitatively studied.