[10p-W351-1~9] CS.8 Code-sharing Session of 9.4 & 12.3 & M

[10p-W351-5] ZT enhancement and development of planar-type silicon thermoelectric devices by nano-patterning

〇Ryoto Yanagisawa¹, Patrick Ruther², Oliver Paul², Masahiro Nomura^1,3 (1.IIS Univ. of Tokyo, 2.IMTEK Univ. of Freiburg, 3.PRESTO JST)

Keywords:thermoelectrics, silicon, energy harvester

In this report, we improved the thermoelectric properties of poly-Si membranes and developed planar-type thermoelectric devices by nano-patterning. By making the phononic crystal nanostructures with considering phonon mean free path of silicon, thermal conductivity decreased and ZT is improved. Next, we fabricated planar-type thermoelectric devices on SOI wafer with lithography processes and demonstrated the power enhancement of devices by nano-patterning. We also made the larger-area devices by using nanoimprint lithography and achieved much higher performance.