4:45 PM - 5:00 PM
△ [11p-W351-14] Time-resolved Simulation of the Negative Capacitance emerging at the Ferroelectric/Semiconductor Hetero-Junction
Keywords:Negative capacitance
Recently, the power consumption of integrated circuits has increased due to the limitation of scaling of the voltage threshold. To solve this issue, it is necessary to overcome the Boltzmann tyranny which exhibits a limit of subthreshold swing of 60 mV/decade at 300 K. Negative capacitance FET (NCFET) is receiving increased attention because of the capability of overcoming the limitation by using NC effect of ferroelectric materials. A number of papers have demonstrated sub-60 mV/decade switching in ferroelectric-gate FETs. However, physical nature of emerging NC in ferroelectric-gate FET have not been clarified. In this paper, we simulated the dynamic electrical behaviors of metal-ferroelectric- semiconductor (MFS) capacitor in order to investigate the physical nature and the influence of the difference in ferroelectric properties on the electrical behavior of an MFS capacitor.