[9p-S221-1~15] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

△ [9p-S221-12] In-situ fabrication of Ge MOS structure with surface flattening RTA

〇(B)Hiroto Ishii^1,2, Hiroyuki Ishii², Wen Hsin Chang², Yukinori Morita², Akira Endou¹, Hiroki Fufishiro¹, Tatsurou Maeda^1,2 (1.TUS, 2.AIST)

Keywords:semiconductor, germanium, surface flattening

Since it is very difficult to control the interface quality with the high-k material oxide in Ge, more complicated interface formation technique than Si is required. In this work, Ge substrate is planarized by heat treatment with RTA and the high-k / metal electrode film is subsequently deposited for in-situ fabrication of Ge MOS structure.