The 66th JSAP Spring Meeting, 2019

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13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[9p-S221-1~15] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Sat. Mar 9, 2019 1:45 PM - 5:45 PM S221 (S221)

Jiro Ida(Kanazawa Inst. of Tech.), Noriyuki Taoka(AIST)

3:00 PM - 3:15 PM

▼ [9p-S221-6] Steep Slope (<60mV/dec) and Hysteresis Characteristics in Junctionless SOI Transistors
at Low Drain Voltage of 50mV

〇(D)Minju Ahn1, Kiyoshi Takeuchi1, Takuya Saraya1, Masaharu Kobayashi1, Toshiro Hiramoto1 (1.Institute of Industrial Science, University of Tokyo)

Keywords:Junctionless, Steep subthreshold slope

In this paper, we report steep subthreshold slope (SS) below 60mV/dec in junctionless SOI transistor at low drain voltage of 50mV, where the impact ionization (II) is negligible. The relationships among SS, drain voltage, hysteresis and scanning speed are shown and the origin of steep SS is discussed.