The 66th JSAP Spring Meeting, 2019

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[9p-S221-1~15] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Sat. Mar 9, 2019 1:45 PM - 5:45 PM S221 (S221)

Jiro Ida(Kanazawa Inst. of Tech.), Noriyuki Taoka(AIST)

2:45 PM - 3:00 PM

[9p-S221-5] Device Physics for Tunnel-FET Utilizing Trap-Assisted Tunneling: "TAT-FET"

Michiru Hogyoku1, Kentaro Kukita1, Tadayoshi Uechi1, Takashi Izumida1, Hiroyoshi Tanimoto1, Nobutoshi Aoki1, Seiji Onoue1 (1.Toshiba Memory Corp.)

Keywords:tunnel-FET, trap-assisted tunneling, small polaron

Tunnel-FET utilizing Band-to-Band Tunneling (BTBT) is expected as a candidate for a steep switching device suitable for low voltage operation. On the other hand, Trap-Assisted Tunneling (TAT) is widely known as a phenomenon similar to BTBT, and Tunnel-FET utilizing this TAT in place of BTBT (TAT-FET) has already been studied. However, comprehensive reports on the principle of TAT-FET are not known. In this report, we consider the principle of TAT-FET, and clarify what kind of traps is suitable for TAT-FET that we aim for and what kind of traps is not suitable for TAT-FET.