[12a-PB4-1~13] 13.5 デバイス／配線／集積化技術

▲ [12a-PB4-10] Power delay analysis of half and full adder circuits using GAA CNTFET with different chirality and channel

〇(DC)Chitra Pandy¹、Singh Rohitkumar¹、V N Ramakrishnan²、Hidenori Mimura¹ (1.Shizuoka University、2.VIT University)

キーワード：Circuit design, GAA CNTFET, Adder

This work describes the analysis of half-adder and full-adder circuits using GAA-CNTFET which is basic element for digital circuits. As scaling down of transistors have become the major concern these days, it has led to the problems such as short channel effects (SCEs), leakage current, high power consumption. To deal with these problems, CNTFETs are used which have proved itself as a promising device in the world of electronics. The property called as “Ballistic Transport” made it even popular as it led to the highly efficient conductivity of the current in the device. It is also regarded as the best replacement for MOSFETs. The transient analysis, power analysis, delay measurement calculations is carried out in this work for full adder and half adder for different chiralities with different channels. Results shows that combination of Single Chirality Double Channel (SCDC) and Double Chirality Double Channel (DCDC) gives the efficient PDP in terms of performance of the circuit designed.