The 67th JSAP Spring Meeting 2020

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[13p-A305-1~13] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Fri. Mar 13, 2020 1:45 PM - 5:45 PM A305 (6-305)

Osamu Nakatsuka(Nagoya Univ.), Kazuhiko Endo(AIST)

4:15 PM - 4:30 PM

[13p-A305-8] First demonstration of (111) Ge-on-insulator n-channel MOSFET fabricated by smart-cut technology

〇(D)CheolMin Lim1, Ziqiang Zhao1, Kei Sumita1, Kasidit Toprasertpong1, Mitsuru Takenaka1, Shinichi Takagi1 (1.Tokyo Univ.)

Keywords:Ge-on-insulator, Smart-cut, (111)

A high-performance Ge-on-insulator (GOI) n-channel MOSFET (nMOSFET) is required to establish the Ge CMOS technology. Here, (111) surface orientation has high potential for Ge nMOSFETs because of the low effective mass, indicating that (111) GOI nMOSFETs are promising. However, there is no report on the operation of (111) GOI nMOSFETs until now, because of the difficulty in preparing (111) GOI substrates. Recently, we have reported the successful fabrication of (111) GOI wafers by the smart-cut technology. In this work, we demonstrate the operation of (111) GOI nMOSFETs using the GOI substrates fabricated by the smart-cut process. Here, the solid-state diffusion process for n+/p junction formation in GOI is examined and optimized.