The 67th JSAP Spring Meeting 2020

Presentation information

Oral presentation

13 Semiconductors » 13.4 Si processing /Si based thin film / MEMS / Equipment technology

[14a-A305-1~11] 13.4 Si processing /Si based thin film / MEMS / Equipment technology

Sat. Mar 14, 2020 9:00 AM - 12:00 PM A305 (6-305)

Kuniyuki Kakushima(Tokyo Tech)

10:00 AM - 10:15 AM

[14a-A305-5] Sidewall planarization in Bosch process

Hiroyuki Tanaka1,2, Hisato Ogiso1,2, Shizuka Nakano1,2, Yoshiyuki Nozawa2,3, Toshihiro Hayami2,3, Khumpuang Sommawan1,2, Shiro Hara1,2 (1.AIST, 2.MINIMAL, 3.SPPT)

Keywords:Bosch Process, Minimal, Deep RIE

One of the features of the Bosch process is that it has a very high selectivity ratio to mask. Particularly, when the resist edge portion is wavy, there is a problem that the resist edge portion appears as a vertical stripe pattern reflecting the waving in the etching progress direction on the etching side wall surface. On the other hand, when the interface between the mask and the Si substrate was sputtered with Ar plasma, the flatness of the etched side surface was improved. Careful fabrication of the mask was effective in performing high quality deep etching.