The 74th JSAP Autumn Meeting,2013

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Poster presentation

13. Semiconductors A (Silicon) » 13.5 Si process technology

[19a-P5-1~14] 13.5 Si process technology

Thu. Sep 19, 2013 9:30 AM - 11:30 AM P5 (Davis Memorial Auditorium)

9:30 AM - 11:30 AM

△ [19a-P5-4] Self-Aligned Embedded Metal Double-Gate Low-Temperature Poly-Si TFT (2)

○Shun Sasaki1, Akito Hara1 (Tohoku Gakuin Univ.1)

Keywords:poly-Si,TFT,double-gate