[19a-C8-1~12] 13.6 Siデバイス／集積化技術

▲ [19a-C8-10] Performance Degradation Due to Drain-Induced Barrier Lowering in Ultra-Low Supply Voltage CMOS Circuits Operating in Subthreshold Region

^○鄭承旻，水谷朋子，平本俊郎 (東大生研)

キーワード：Low power CMOS,Drain-induced barrier lowering