[19a-C8-1~12] 13.6 Silicon devices / Integration technology

Thu. Sep 19, 2013 9:00 AM - 12:15 PM C8 (TC3 2F-201)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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9:00 AM - 9:15 AM

[19a-C8-1] [Young Scientist Oral Presentation Award Speech](15 min.) Drain-Current Fluctuation during Dynamic Gate Bias in Si MOSFETs due to Random Telegraph Noise

^○Wei Feng^1,2, Keisaku Yamada^1,2, Kenji Ohmori^1,2 (Univ. of Tsukuba¹, JST-CREST²)

9:15 AM - 9:30 AM

[19a-C8-2] Analysis of Multi-Trap Random Telegraph Noise Using Trap Charging History (I):Judgment of the Number and Charging Conditions of the Oxide Traps

^○Toshiaki Tsuchiya¹, Naoyoshi Tamura², Akihito Sakakidani², Kenichiro Sonoda², Masayuki Kamei², Shinya Yamakawa², Sumio Kuwabara² (Shimane Univ.¹, STARC²)

9:30 AM - 9:45 AM

[19a-C8-3] Analysis of Multi-Trap Random Telegraph Noise Using Trap Charging History (II):Characterization of Each Individual Oxide Trap

^○Toshiaki Tsuchiya¹, Naoyoshi Tamura², Akihito Sakakidani², Kenichiro Sonoda², Masayuki Kamei², Shinya Yamakawa², Sumio Kuwabara² (Shimane Univ.¹, STARC²)

9:45 AM - 10:00 AM

△ [19a-C8-4] A Study on Strain Induced Random Telegraph Noise Suppression in pMOSFETs

^○JIEZHI CHEN¹, Yusuke Higashi¹, Izumi Hirano¹, Yuichiro Mitani¹ (Toshiba R&D Center¹)

10:00 AM - 10:15 AM

△ [19a-C8-5] Dependence of soft error rate in SOI SRAM on generated charge under buried oxide by high energy ion probes

^○Masatoshi Hazama¹, Satoshi Abo¹, Fujio Wakaya¹, Takahiro Makino², Shinobu Onoda², Takeshi Ohshima², Toshiaki Iwamatsu³, Hidekazu Oda³, Mikio Takai¹ (CQSTEC¹, JAEA², Renesas Electronics Corp.³)

Break (10:15 AM - 10:30 AM)

10:30 AM - 10:45 AM

[19a-C8-6] Analysis of current-onset voltage fluctuation for FinFETs : Influence of work function variation of metal gates

^○Takashi Matsukawa¹, Yongxun Liu¹, Junichi Tsukada¹, Kazuhiko Endo¹, Hiromi Yamauchi¹, Yuki Ishikawa¹, Shinichi O'uchi¹, Wataru Mizubayashi¹, Hiroyuki Ota¹, Shinji Migita¹, Yukinori Morita¹, Meishoku Masahara¹ (AIST¹)

10:45 AM - 11:00 AM

[19a-C8-7] Reconsideration of the Threshold Voltage Variability Estimated with Pair Transistor Cell Array

^○Kazuo Terada¹, Katsuhiro Tsuji¹ (Hiroshima City Univ.¹)

11:00 AM - 11:15 AM

▲ [19a-C8-8] Recovery Behaviors of |Vth| Shift of pFETs by High-Voltage OFF-State and ON-State Stress for Post-Fabrication SRAM Cell Stability Self-Improvement

^○Nurul Ezaila Alias¹, Anil Kumar¹, Takuya Saraya¹, Shinji Miyano², Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, STARC²)

11:15 AM - 11:30 AM

[19a-C8-9] Reduced Cell Current Variability in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells at Supply Voltage of 0.4V

^○Tomoko Mizutani¹, Yoshiki Yamamoto², Hideki Makiyama², Hirofumi Shinohara², Toshiaki Iwamatsu², Hidekazu Oda², Nobuyuki Sugii², Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, LEAP²)

11:30 AM - 11:45 AM

▲ [19a-C8-10] Performance Degradation Due to Drain-Induced Barrier Lowering in Ultra-Low Supply Voltage CMOS Circuits Operating in Subthreshold Region

^○SeungMin Jung¹, Tomoko Mizutani¹, Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹)

11:45 AM - 12:00 PM

[19a-C8-11] Analysis of Drain Voltage Dependence of Drain Induced Barrier Lowering (DIBL)

^○Mitsuaki Mitsuaki¹, Tomoko Mizutani¹, Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹)

12:00 PM - 12:15 PM

[19a-C8-12] SRAM Cell Stability Parameter: Noise Margin or Vmin?

^○Anil Kumar¹, Takuya Saraya¹, Shinji Miyano², Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, STARC²)