[19p-C9-1~7] 13.7 Simulation

[19p-C9-5] Improve of Tunnel FET performance using narrow bandgap semiconductor silicide/Si hetero-structure source electrode

^○Hiroki Hasegawa¹, Yan Wu¹, Kuniyuki Kakushima², Yoshinori Kataoka², Akira Nishiyama², Nobuyuki Sugii², Hitoshi Wakabayashi², Kazuo Tsutsui², Kenji Natori¹, Hiroshi Iwai¹ (Tokyo Tech.FRC¹, Tokyo Tech.IGSSE²)

Keywords:トンネルFET,マグネシウムシリサイド,サブスレッショルド係数