[28a-G9-1~11] 13.6 Silicon devices / Integration technology

Thu. Mar 28, 2013 9:00 AM - 11:45 AM G9 (B5 2F-2203)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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[28a-G9-1] A Methodology of Control Gate Length, Spacing and Stacked Layer Number Design for 3D-Stackable BiCS Type NAND Flash Memory

^○Kousuke Miyaji¹, Yuki Yanagihara², Ken Takeuchi¹ (Chuo Univ.¹, Univ. of Tokyo²)

[28a-G9-2] Unified Solid-State-Storage Architecture

^○Shuhei Tanakamaru^1,2, Masafumi Doi¹, Ken Takeuchi¹ (Chuo Univ.¹, Univ. of Tokyo²)

[28a-G9-3] Reliability Evaluation Results of Unified Solid-State Storage

^○Masafumi Doi¹, Shuhei Tanakamaru^1,2, Ken Takeuchi¹ (Chuo Univ.¹, Univ. of Tokyo²)

[28a-G9-4] Reliability of the 2Xnm TLC NAND Flash Memory

^○Yoshihiko Yamane¹, Shogo Hachiya¹, Shuhei Tanakamaru^1,2, Ken Takeuchi¹ (Chuo Univ.¹, Univ of Tokyo.²)

[28a-G9-5] Application of Oxide Layer Formed by Nitric Acid Oxidation of Si (NAOS) Method to Ultra-low Power CPU on Glass and Eternal Memory “Digital Rosetta Stone”

^○Taketoshi Matsumoto¹, Tomoki Akai¹, Shigeki Imai¹, Hikaru Kobayashi¹ (ISIR, Osaka Univ., CREST-JST¹)

[28a-G9-6] Low Power 6T-SRAM with a Carrier-Injection Scheme to Simultaneously Pinpoint and Repair Disturb Fails

^○Kousuke Miyaji¹, Shinji Miyano², Ken Takeuchi¹ (Chuo Univ.¹, STARC²)

[28a-G9-7] Performance and design of pseudo-spin-MOSFET and nonvolatile SRAM cell using nano-CMOS technology

^○Yusuke Shuto^1,3,4, Shuu'ichirou Yamamoto^2,3, Satoshi Sugahara^1,3 (ISEL, Tokyo Inst. Tech.¹, Dept. Info. Processing, Tokyo Inst. Tech.², CREST, JST³, KAST⁴)

[28a-G9-8] Proposal of nonvolatile dual-port SRAM cell using pseudo-spin-MOSFETs and its nonvolatile PG application

Shuu'ichirou Yamamoto¹, ^○Yusuke Shuto^2,3, Satoshi Sugahara^1,2 (IGS, Tokyo Inst. Tech.¹, ISEL, Tokyo Inst. Tech.², KAST³)

[28a-G9-9] ▲Stress Condition Dependence of |Vth| Shift and Variability in OFF-State Stress in pFETs for Post-Fabrication Self-Improvement of SRAM Stability

^○Nurul Ezaila Alias¹, Anil Kumar², Saraya Takuya³, Miyano Shinji⁴, Hiramoto Toshiro⁵ (Univ. of Tokyo¹, Univ. of Tokyo², Univ. of Tokyo³, STARC⁴, Univ. of Tokyo⁵)

[28a-G9-10] Influence of Vth Variability on 0.4V-Operation in Silicon-on-Thin-Buried Oxide (SOTB) CMOS SRAM

^○Hirofumi Shinohara¹, Yoshiki Yamamoto¹, Hideki Makiyama¹, Toshiaki Iwamatsu¹, Hidekazu Oda¹, Shiro Kamohara¹, Nobuyuki Sugii¹, Yasuo Yamaguchi¹, Tomoko Mizutani², Toshiro Hiramoto² (LEAP¹, University of Tokyo²)

[28a-G9-11] Statistical Analysis of Subthreshold Swing Variability in Fully Depleted Silicon-on-Thin-BOX (SOTB) MOSFETs

^○Tomoko Mizutani¹, Yoshiki Yamamoto², Hideki Makiyama², Hirofumi Shinohara², Toshiaki Iwamatsu², Hidekazu Oda², Nobuyuki Sugii², Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, LEAP²)

Session information

[28a-G9-1~11] 13.6 Silicon devices / Integration technology