Low Dit La2O3/In0.53Ga0.47As Gate Stack scaled to sub-nm CET

Daryoush Hassan Zadeh

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Oral presentation

13. Semiconductors A (Silicon) » 13.2 Insulator technology

[18p-D8-1~15] 13.2 Insulator technology

Tue. Mar 18, 2014 1:30 PM - 5:30 PM D8 (D215)

5:00 PM - 5:15 PM

△ [18p-D8-14] Low D_it La₂O₃/In_0.53Ga_0.47As Gate Stack scaled to sub-nm CET

^○（PC）Daryoush Hassan Zadeh¹, Hiroshi Oomine¹, Kuniyuki Kakushima², Yoshinori Kataoka², Akira Nishiyama², Nobuyuki Sugii², Hitoshi Wakabayashi², Kazuo Tsutsui², Kenji Natori¹, Hiroshi Iwai¹ (Tokyo Tech. FRC¹, Tokyo Tech. IGSSE²)

Keywords:InGaAs,high-k,Dit

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Presentation information

[18p-D8-1~15] 13.2 Insulator technology

△ [18p-D8-14] Low Dit La2O3/In0.53Ga0.47As Gate Stack scaled to sub-nm CET

△ [18p-D8-14] Low D_it La₂O₃/In_0.53Ga_0.47As Gate Stack scaled to sub-nm CET