2017年第78回応用物理学会秋季学術講演会

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一般セッション(口頭講演)

13 半導体 » 13.4 Si系プロセス・Si系薄膜・配線・MEMS・集積化技術

[6p-C21-1~20] 13.4 Si系プロセス・Si系薄膜・配線・MEMS・集積化技術

2017年9月6日(水) 13:45 〜 19:00 C21 (C21)

角嶋 邦之(東工大)、曽根 正人(東工大)

17:00 〜 17:15

[6p-C21-13] MEMS Piezo-resistive Accelerometer Fabricated by Full Minimal Fab Process

AnhTuan Phan1,2、Hiroyuki Tanaka1,3、Norio Umeyama1,3、Noriko Miura1,3、Khumpuang Sommawan1,3、Shiro Hara1,3 (1.Minimal Fab、2.SHTPLabs、3.AIST)

キーワード:MEMS Piezo-resistive Accelerometer, Minimal Fab

In the semiconductor industry, the trend of manufacturing integrated circuits (IC) is to enlarge silicon wafer size from 300 mm to 450 mm. The transition to the next larger wafer size enables the fabrication of more chip per wafer. However, it causes a larger investment cost. The resulting increase in price will certainly push up the research and development cost of new semiconductor devices. A novel semiconductor manufacturing system called “minimal fab” has been developed for customized semiconductor devices and microelectromechanical systems (MEMS) with low costs [1]. Micro-needle structure was the first micro-structure that was successfully fabricated using the minimal fab [2]. In this work, for the first time, we develop a MEMS piezo-resistive accelerometer in which the fabrication process is fully compatible with both IC process technology and bulk micromachining technology.