[6p-C21-1~20] 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

[6p-C21-15] Characterization of CMP Planarization Process in Minimal Fab

〇Norio Umeyama^1,2, Noriko Miura², Fumito Imura^1,2, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL)

Keywords:Minimal Fab, CMP

asic evaluation of the planarization process was carried out using a minimal CMP tool. An irregular pattern with a different size was formed on a half-inch Si wafer and planarization was attempted. All processes used minimal equipment. From the surface profile measurement results, almost flattening was achieved when the width was 15 μm or less. On the day we will discuss about how flattening can be done with minimal CMP equipment.