The 78th JSAP Autumn Meeting, 2017

Presentation information

Oral presentation

13 Semiconductors » 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

[6p-C21-1~20] 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

Wed. Sep 6, 2017 1:45 PM - 7:00 PM C21 (C21)

Kuniyuki Kakushima(Titech), Masato Sone(Titech)

6:00 PM - 6:15 PM

[6p-C21-17] Half-inch Wafers for New Materials Processing Model

Norio Umeyama1,2, Takaaki Sakai3, Atsushi Kajikura3, Kouichiro Ichikawa3, Sommawan Khumpuang1,2, Shiro Hara1,2 (1.AIST, 2.MINIMAL, 3.Fujikoshi Machinery)

Keywords:Minimal Fab, SOI, GaAs

For minimal fab, it is possible to manufacture semiconductor devices using half-inch wafers using a human-sized machine in a clean room-less environment, but in half-inch sizes for materials that are difficult to increase in diameter, easy to develop device application development. In this report, we describe half-inch development situation for wafer materials other than silicon, propose and discuss process model for making new material into half-inches.