2018年第79回応用物理学会秋季学術講演会

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13 半導体 » 13.1 Si系基礎物性・表面界面・シミュレーション

[21p-135-1~16] 13.1 Si系基礎物性・表面界面・シミュレーション

2018年9月21日(金) 13:00 〜 17:15 135 (135)

上野 智雄(農工大)、嵯峨 幸一郎(ソニー)

15:45 〜 16:00

[21p-135-11] Lateral etching of HfN0.5 narrow line utilizing diluted HF solution

〇(M1)Yizhe Ding1、Rengie Mark D Mailig1、Sohya Kudoh1、Shun-ichiro Ohmi1 (1.Tokyo Tech)

キーワード:wet etching, narrow line

The so-called high-κ gate dielectrics are regarded as the most promising candidates to overcome the limitations of transistor scaling, such as equivalent-oxide-thickness (EOT) and gate length (Lg) scaling. We have reported that 0.5 nm EOT utilizing bilayer HfNx gate insulators with in-situ formed HfN0.5 gate electrode. In this paper, the lateral etching of HfN0.5 gate electrode utilizing diluted HF (DHF) solution was investigated. The lateral etching rate of 1.1 µm/min was confirmed by 4 µm L/S pattern. Moreover, the precise control of lateral etching for HfN0.5 gate electrode was realized which would be suitable for narrow gate formation.