2018年第79回応用物理学会秋季学術講演会

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13 半導体 » 13.1 Si系基礎物性・表面界面・シミュレーション

[21p-135-1~16] 13.1 Si系基礎物性・表面界面・シミュレーション

2018年9月21日(金) 13:00 〜 17:15 135 (135)

上野 智雄(農工大)、嵯峨 幸一郎(ソニー)

14:45 〜 15:00

[21p-135-8] Effect of Conduction Band Offset on Breakdown Voltage at SiO2/4H-SiC (000-1) studied by Hard X-ray Photoelectron Spectroscopy

〇(D)Efi Dwi Indari1,2、Yoshiyuki Yamashita1,2、Takahiro Nagata1、Shigenori Ueda1,3、Ryu Hasunuma4、Kikuo Yamabe4 (1.NIMS、2.Kyushu Univ、3.SPring-8、4.Univ of Tsukuba)

キーワード:breakdown voltage, conduction band offset, SiO2/4H-SiC (000-1)

We investigated the effect of conduction band offset (ΔEc) on the breakdown voltage upon SiO2/4H-SiC (000-structures by means of hard x-ray photoelectron spectroscopy. For electrical measurement of metal/SiO2/4H-SiC (000-1) structures, the breakdown voltage increases with larger ΔEc. SiO2 prepared by dry oxidation procedure exhibits largest ΔEc, while wet oxidation procedure exhibits smallest ΔEc. Oxygen annealing performed after wet oxidation was effective for an increase of ΔEc, yields higher breakdown voltage. Consequently, larger ΔEc results in lower leakage current.