The 79th JSAP Autumn Meeting, 2018

Presentation information

Print

Oral presentation

13 Semiconductors » 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

[21p-233-1~14] 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

Fri. Sep 21, 2018 1:00 PM - 4:45 PM 233 (233)

Kuniyuki Kakushima(Tokyo Tech), Yan Wu(Nihon University)

1:45 PM - 2:00 PM

[21p-233-4] Fabrication of 2-input NAND gate by Minimal TiN SOI-CMOS process

〇Koichi Morikawa1, Kozo Takeuchi1, Yasushi Igarashi1, Hiroyuki Shindo1, Somawan Khumpuang2, Shiro Hara2 (1.JAXA, 2.AIST)

Keywords:minimalfab, 2-input NAND gate