Relaxation of Self-Heating-Effect for Lateral-Stacked Silicon-NW FETs with Source/Drain-Recessed Contact Structure

Eisuke Anju; Iriya Muneta; Kuniyuki Kakushima; Kazuo Tsutsui; Hitoshi Wakabayashi

Presentation information

Symposium (Oral)

Symposium » Semiconductor Device Simulation: Applications and Future Perspectives

[18p-A202-1~15] Semiconductor Device Simulation: Applications and Future Perspectives

Sun. Mar 18, 2018 1:15 PM - 6:40 PM A202 (54-202)

Nobuya Mori(Osaka Univ.), Koichi Fukuda(AIST), Akira Hiroki(Kyoto Inst. of Tech.), Kenichiro Sonoda(Renesas), Nobutoshi Aoki(Toshiba Memory)

5:30 PM - 5:45 PM

△ [18p-A202-11] Relaxation of Self-Heating-Effect for Lateral-Stacked Silicon-NW FETs with Source/Drain-Recessed Contact Structure

〇Eisuke Anju¹, Iriya Muneta¹, Kuniyuki Kakushima¹, Kazuo Tsutsui¹, Hitoshi Wakabayashi¹ (1.Tokyo Tech)

Keywords:nanowire, self-heating-effect

Gate-All-Around (GAA) nanowire (NW) FETs offer an optimal electrostatic control, thereby expected one of the promising candidates in sub-10-nm technology nodes. Maximizing the drive current per footprint using lateral stacked- or vertical NW has been considered lately. However, in the GAA-NWs and/or SOI technology, self-heating-effects (SHEs) is becoming serious problem. In this work, in order to mitigate the SHEs in GAA-NW FETs, we investigate lateral stacked-NW on bulk-fin with recessed contact structure.