The 80th JSAP Autumn Meeting 2019

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[18p-B11-1~14] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Wed. Sep 18, 2019 1:15 PM - 5:00 PM B11 (B11)

Masaharu Kobayashi(Univ. of Tokyo), Shinji Migita(AIST), Hitoshi Wakabayashi(Tokyo Tech)

2:30 PM - 2:45 PM

[18p-B11-6] Experimental demonstration of n-/p-TFET operations in a single ZnSnO/SiGe bilayer structure

Kimihiko Kato1,2, Kwangwon Jo2, Hiroaki Matsui2, Hitoshi Tabata2, Takahiro Mori1, Yukinori Morita1, Takashi Matsukawa1, Mitsuru Takenaka2, Shinichi Takagi2 (1.AIST, 2.Univ. of Tokyo)

Keywords:tunneling FET, ZnSnO, SiGe

We are proposing bilayer tunneling field effect transistors (TFETs) by utilizing an n-type oxide semiconductor channel and a p-type group-IV semiconductor source for ultra-low power switching devices. In this study, we succeeded p-type TFET operation by utilizing hetero tunneling junction with p-type SiGe layer and n-type ZnSnO layer, fabricated on SiGe-on-insulator substrate. Additionally, we demonstrated both n- and p-TFET operations in a single ZnSnO/SiGe bilayer TFET structure by changing the gate electrodes between the top and back ones, and it is attractive result for realizing complementary circuits with bilayer TFETs.