The 80th JSAP Autumn Meeting 2019

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[18p-B11-1~14] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Wed. Sep 18, 2019 1:15 PM - 5:00 PM B11 (B11)

Masaharu Kobayashi(Univ. of Tokyo), Shinji Migita(AIST), Hitoshi Wakabayashi(Tokyo Tech)

2:15 PM - 2:30 PM

[18p-B11-5] Improved subthreshold characteristics of p-type poly-Si junctionless transistor by utilizing optimized channel structure

〇(D)Minju Ahn1, Takuya Saraya1, Masaharu Kobayashi1, Toshiro Hiramoto1 (1.Institute of Industrial Science, University of Tokyo)

Keywords:Poly-Si, Junctionless, Transistor

In this report, we have experimentally investigated the subthreshold characteristics of p-type poly-Si junctionless transistors with optimized channel structure. The fabricated transistors exhibit excellent electrical characteristics in terms of steep subthreshold slope (~63mV/dec.), high on/off current ratio (~1.4x108), hysteresis (~ 0V) and low off-state leakage current (<1x10-13A).