[16p-A403-1~20] 13.5 デバイス／配線／集積化技術

▼ [16p-A403-8] A Simulation Study on Memory Characteristics of Oxide-Semiconductor Channel Antiferroelectric FETs Using Half-Loop Hysteresis

〇(M2)Xingyu Huang¹、Yuki Itoya¹、Zhuo Li¹、Takuya Saraya¹、Toshiro Hiramoto¹、Masaharu Kobayashi^1,2 (1.IIS., Univ. of Tokyo、2.d.lab, Univ. of Tokyo)

キーワード：Oxide semiconductor channel, AFeFET, Half-loop hysteresis

HfO₂-based ferroelectric FET memories have attracted much attention due to its CMOS capability and potential low power consumption. Particularly, oxide semiconductor (OS) such as IGZO channel based FeFETs have been recently demonstrated and show great potential because of its high mobility and no low-k interfacial layer formation in 3D structures. However, OS is typically n-type channel material which hardly generates minority hole carriers, causing the weak erase issue in OS channel FeFETs. Previously, antiferroelectric FETs (AFeFETs) have been proposed for efficient erase operation with OS channel by using half-loop hysteresis. But the memory characteristics of OS channel AFeFETs have not been fully discussed yet. In this work, we developed a compact AFeFET model, studied the memory characteristics of OS channel AFeFETs by varying design parameters, and provided design guide for potential memory applications.