Oral presentation

[16a-A403-1~10] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Thu. Mar 16, 2023 9:00 AM - 11:45 AM A403 (Building No. 6)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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9:00 AM - 9:15 AM

[16a-A403-1] Coulomb collision of single electrons in silicon double single-electron pumps

〇Gento Yamahata¹, Nathan Johnson¹, Akira Fujiwara¹ (1.NTT BRL)

9:15 AM - 9:30 AM

△ [16a-A403-2] Characterization of Charge Noise in an nMOS Si Quantum Dot using RF Reflectometry

〇Yuto Arakawa¹, Kazuma Nakagoe¹, Ryutaro Matsuoka¹, Ryuta Tsuchiya², Toshiyuki Mine², Digh Hisamoto², Hiroyuki Mizuno², Raisei MIzokuchi¹, Jun Yoneda¹, Tetsuo Kodera¹ (1.Tokyo Tech, 2.R&D Group, Hitachi Ltd.)

9:30 AM - 9:45 AM

[16a-A403-3] Characterization of Detuning Noise in a Si Quantum Dot

Kazuma Nakagoe¹, 〇Yuto Arakawa¹, Ryutaro Matsuoka¹, Ryuta Tsuchiya², Toshiyuki Mine², Digh Hisamoto², Hiroyuki Mizuno², Raisei Mizokuchi¹, Jun Yoneda¹, Tetsuo Kodera¹ (1.Tokyo Tech, 2.R&D Group, Hitachi Ltd.)

9:45 AM - 10:00 AM

△ [16a-A403-4] Design and evaluation of single-stage matching circuits suitable for RF reflectometry of a physically defined quantum dot

〇(M1)Ryo Matsuda¹, Jun Kamioka¹, Raisei Mizokuchi¹, Jun Yoneda¹, Tetsuo Kodera¹ (1.Tokyo Tech Inst.)

10:00 AM - 10:15 AM

[16a-A403-5] Fabrication and Low Temperature Characteristics of Silicon Double Quantum Dots

〇(M2)Junoh Kim¹, Tomoko Mizutani¹, Takuya Saraya¹, Hiroshi Oka², Takahiro Mori², Masaharu Kobayashi^1,3, Toshiro Hiramoto¹ (1.IIS, Univ. of Tokyo, 2.AIST, 3.d.lab, Univ. of Tokyo)

10:30 AM - 10:45 AM

[16a-A403-6] Magnetospectroscopy of electron spins in a multi-electron silicon quantum dot

〇Raisei Mizokuchi¹, Go Sakamoto¹, Chihiro Kondo¹, Ryutaro Matsuoka¹, Ryuta Tsuchiya², Toshiyuki Mine², Digh Hisamoto², Hiroyuki Mizuno², Jun Yoneda¹, Tetsuo Kodera¹ (1.Tokyo Tech, 2.R&D Group, Hitachi Ltd.)

10:45 AM - 11:00 AM

[16a-A403-7] SPICE compact model of spin qubits using FinFET focusing on single-electron tunnelin

Elias Perez^1,2, Teresa O-Guerrero², 〇Tetsufumi Tanamoto¹ (1.Teikyo Univ., 2.Univ. Panamericana)

11:00 AM - 11:15 AM

[16a-A403-8] Improvement of sensitivity in room temperature operating quantum magnetic sensors using spin blockades

〇(PC)Yoshisuke Ban¹, Kimihiko Kato², Shota Iizuka², Shigenori Shigenori², Koji Ishibashi¹, Satoshi Moriyama³, Takahiro Mori², Keiji Ono¹ (1.RIKEN, 2.AIST, 3.Tokyo Denki Univ.)

11:15 AM - 11:30 AM

[16a-A403-9] Direct observation of electron capture processes in amphoteric defect states achieved by charge pumping in individual defects at MOS interface (6) -Lattice relaxation (II)-

〇Toshiaki Tsuchiya¹, Masahiro Hori¹, Yukinori Ono¹ (1.Shizuoka Univ.)

11:30 AM - 11:45 AM

[16a-A403-10] Direct observation of electron capture processes in amphoteric defect states achieved by charge pumping in individual defects at MOS interface (7) - Consideration on τ_D-

〇Toshiaki Tsuchiya¹, Masahiro Hori¹, Yukinori Ono¹ (1.Shizuoka Univ.)

Oral presentation

[16p-A403-1~20] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Thu. Mar 16, 2023 1:00 PM - 6:45 PM A403 (Building No. 6)

Kazuhiko Endo(Tohoku Univ.), Kimihiko Kato(AIST)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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1:00 PM - 1:15 PM

[16p-A403-1] The 14th Silicon Technology Division Paper Award / Young Researcher Award Ceremony

〇Kazuhiko Endo^1,2 (1.Chief Secretary of Silicon Technology Division, 2.Tohoku Univ.)

1:15 PM - 1:45 PM

[16p-A403-2] [The 14th Silicon Technology Division Paper Award Speech] Optimum Channel Design of Extremely-Thin-Body nMOSFETs Utilizing Anisotropic Valley—Robust to Surface Roughness Scattering

〇Kei Sumita¹, Chia-Tsong Chen¹, Kasidit Toprasertpong¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.Univ. Tokyo)

1:45 PM - 2:15 PM

[16p-A403-3] [The 14th Silicon Technology Division Paper Award Speech] Quantum Non-demolition Readout of a Silicon Spin Qubit

〇Jun Yoneda¹, Kenta Takeda², Akito Noiri², Takashi Nakajima², Sen Li², Jun Kamioka¹, Tetsuo Kodera¹, Seigo Tarucha² (1.Tokyo Inst. of Tech., 2.RIKEN)

2:15 PM - 2:30 PM

[16p-A403-4] [The 14th Silicon Technology Division Young Researcher Award Speech] ZrS₂ symmetrical-ambipolar FETs with near-midgap TiN film for both top-gate electrode and Schottky-barrier contact

〇Masaya Hamada¹, Kentaro Matsuura¹, Takuya Hamada¹, Iriya Muneta¹, Kuniyuki Kakushima¹, Issei Tsutsui¹, Hitoshi Wakabayashi¹ (1.Tokyo Tech.)

2:30 PM - 2:45 PM

[16p-A403-5] [The 14th Silicon Technology Division Young Researcher Award Speech] Structural and electrical characteristics of ion-induced Si damage during atomic layer etching

〇Akiko Hirata¹, Masanaga Fukasawa¹, Katsuhisa Kugimiya¹, Kazuhiro Karahashi², Satoshi Hamaguchi², Yoshiya Hagimoto¹, Hayato Iwamoto¹ (1.Sony Semiconductor Solutions Corp., 2.Osaka Univ.)

2:45 PM - 3:00 PM

▲ [16p-A403-6] 3D NAND Memory Operation of Oxide-Semiconductor Channel FeFETs

〇(M2)Junxiang Hao¹, Xiaoran Mei¹, Takuya Saraya¹, Toshiro Hiramoto¹, Masaharu Kobayashi^1,2 (1.IIS, Univ. of Tokyo, 2.d.lab, Univ. of Tokyo)

3:00 PM - 3:15 PM

[16p-A403-7] Energy-efficient Annealing Process of HfO₂-based Ferroelectric Capacitor using UV-LED for Green Manufacturing

〇Hirotaka Yamada^1,2, Satoru Furue¹, Takehiko Yokomori¹, Yuki Itoya², Takuya Saraya², Toshiro Hiramoto², Masaharu Kobayashi^2,3 (1.Ushio Inc., 2.IIS, Univ. of Tokyo, 3.d.lab, Univ. of Tokyo)

3:15 PM - 3:30 PM

▼ [16p-A403-8] A Simulation Study on Memory Characteristics of Oxide-Semiconductor Channel Antiferroelectric FETs Using Half-Loop Hysteresis

〇(M2)Xingyu Huang¹, Yuki Itoya¹, Zhuo Li¹, Takuya Saraya¹, Toshiro Hiramoto¹, Masaharu Kobayashi^1,2 (1.IIS., Univ. of Tokyo, 2.d.lab, Univ. of Tokyo)

3:30 PM - 3:45 PM

[16p-A403-9] Simulation Study on the Effects of Charge Traps in a Ferroelectric Tunnel Junction

〇(M2)Jaehyun Kim¹, Takuya Saraya¹, Toshiro Hiramoto¹, Masaharu Kobayashi^1,2 (1.IIS, Univ. of Tokyo, 2.d.lab, Univ. of Tokyo)

4:00 PM - 4:15 PM

[16p-A403-10] Influence of annealing temperature on electrical properties of TiO_x-based ReRAM

〇(B)Kakeru Ikeda¹, Haruki Osawa¹, Shinya Aikawa¹ (1.Kogakuin Univ.)

4:15 PM - 4:30 PM

[16p-A403-11] Ta oxide film growth by electrochemical oxidation method and its application to ReRAM

〇(M1C)Naohito Miyata¹, Yoshiaki Ishii¹, Masao takahashi¹, masahiro Moniwa¹ (1.Tokyo Univ. of Technology)

4:30 PM - 4:45 PM

[16p-A403-12] Fabrication and Evaluation of Resistive Switching Devices Using Selective Surface Oxidation Films of Liquid Metal Alloys

〇(M1)Yuto Katsuma¹, Takahiko Ban¹, Masayoshi Ichimiya¹, Junichi Yanagisawa¹, Shin-ichi Yamamoto² (1.Shiga Prefecture Univ., 2.Ryukoku Univ.)

4:45 PM - 5:00 PM

[16p-A403-13] Molecular Dynamics Simulation of Phase Transition of Nanoscale Molten Salts Surrounded by SiO₂

〇Yusuke Nishimura¹, Yuji Yamanaka¹, Takanobu Watanabe¹ (1.Waseda Univ.)

5:00 PM - 5:15 PM

▲ [16p-A403-14] Tuning of Conductance Values by Si Doping in GeTe for Artificial Synapse Characteristics

〇(D)Shinyoung Kang¹, Mihyeon Kim¹, Shuang Yi^1,2, Daisuke Ando¹, Yuji Sutou¹ (1.Tohoku.Univ, 2.Tohoku.Univ(AIMR))

5:15 PM - 5:30 PM

[16p-A403-15] Step coverage of Al₂O₃ film by ALD using high purity ozone

〇Takayuki Hagiwara¹, Soichiro Motoda¹, Naoto Kameda¹, Ken Nakamura², Hidehiko Nonaka² (1.MEIDEN NPI INC., 2.AIST)

5:30 PM - 5:45 PM

△ [16p-A403-16] Interfacial Analysis of Low Temperature Deposited CVD-SiO₂ for Direct Bonding

〇Hayato Kitagawa¹, Koki Onishi¹, Tomoya Iwata¹, Junya Fuse¹, Akira Uedono², Fumihiro Inoue¹ (1.Yokokoku Univ., 2.Univ. of Tukuba)

5:45 PM - 6:00 PM

△ [16p-A403-17] Kinetics of Dangling Bonds and Open Spaces of SiCN for Surface for Plasma Activated Direct Bonding

〇Sodai Ebiko¹, Koki Onisi¹, Fuya Nagano², Akira Uedono³, Fumihiro Inoue¹ (1.Yokokoku Univ., 2.imec, 3.Univ. of Tsukuba)

6:00 PM - 6:15 PM

▲ [16p-A403-18] Effects of Annealing on Thermal Boundary Resistance of Low-k Interlayer Dielectrics

〇Mao Xu¹, Zhi Cao², Akitoshi Okino¹, Tianzhuo Zhan³ (1.FIRST, Tokyo Tech, 2.Waseda Univ., 3.Toyo Univ.)

6:15 PM - 6:30 PM

[16p-A403-19] Study of Highly Reliable Cu Dual-Damascene Interconnects using Ti Barrier for 3D Flash Memory

〇Junya Wada¹, Akira Nakajima¹, Yoshiki Aizawa¹, Masayuki Kitamura¹, Ryo Tanaka¹, Kotaro Fujii¹, Hisashi Kato¹, Masayoshi Tagami¹, Katsuyuki Sekine¹, Kazuya Ohuchi¹ (1.KIOXIA)

6:30 PM - 6:45 PM

▲ [16p-A403-20] Cu diffusion barrier property evaluation of 1-nm-thick PVD-Co(W) films by time-lag method

〇(D)Yubin DENG¹, Takeshi Momose¹, Yukihiro Shimogaki¹ (1.The Univ. of Tokyo)

Oral presentation

[17a-A403-1~10] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Fri. Mar 17, 2023 9:00 AM - 11:45 AM A403 (Building No. 6)

Kiyoshi Takeuchi(Univ. of Tokyo)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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9:00 AM - 9:15 AM

[17a-A403-1] 1DEG calculation of nanosheet MOSFETs

〇Koichi Fukuda¹, Mariko Ninomiya¹, Junichi Hattori¹ (1.AIST)

9:15 AM - 9:30 AM

[17a-A403-2] Relationship between electron velocity overshoot effects and gate length in Si nanosheet FETs

〇Junichi Hattori¹, Koichi Fukuda¹, Tsutomu Ikegami¹, Yoshihiro Hayashi¹ (1.AIST)

9:30 AM - 9:45 AM

[17a-A403-3] First-Principles Calculation of Electron Effective Mass in Strained Silicon Nanosheet

〇(P)Hikaru Horii¹, Akiko Ueda¹, Yoshihiro Hayashi¹ (1.AIST)

9:45 AM - 10:00 AM

▲ [17a-A403-4] Self-heating and Short-Channel Effect Immunity with Partial-Bottom-Dielectric-Isolation for Gate-All-Around Nano-Sheet FETs

〇(D)Peilong Wang¹, Atsushi Hori¹, Iriya Muneta¹, Takamasa Kawanago¹, Kuniyuki Kakushima¹, Kazuo Tsutsui¹, Hitoshi Wakabayashi¹ (1.Tokyo Institute of Technology)

10:00 AM - 10:15 AM

[17a-A403-5] Interpretation of universality of mobility against effective electric field and coefficient η based on nonlinear model of surface roughness scattering

〇(D)Kei Sumita¹, Kasidit Toprasertpong¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.Univ. Tokyo)

10:30 AM - 10:45 AM

[17a-A403-6] Transient characterization of Steep SS Device “Dual-Gate PN-Body Tied SOI-FET”

〇(M1)Haruki Yonezaki¹, Jiro Ida¹, Takayuki Mori¹ (1.KIT)

10:45 AM - 11:00 AM

[17a-A403-7] Back Bias and Hysteresis Effect of Cryogenic 200 nm SOI MOSFET

〇Takayuki Mori¹, Tatsukichi Sugii¹, Ryusei Ri¹, Hiroshi Oka², Takahiro Mori², Jiro Ida¹ (1.Kanazawa Inst. of Tech., 2.AIST)

11:00 AM - 11:15 AM

[17a-A403-8] Integration Design of 3D CFET SRAM for Extremely Reduced Cell Size

〇WENHSIN CHANG¹, X. R. Yu^2,3, T. C. Hong^2,4, Y. J. Lee^2,4, T. S. Chao⁴, Y. H. Wang³, T. Maeda¹ (1.AIST, 2.TSRI, 3.NCKU, 4.NYCU)

11:15 AM - 11:30 AM

[17a-A403-9] Design of GeSn/GeSiSn resonant tunneling diodes toward room temperature operation

〇Shuto Ishimoto¹, Mitsuo Sakashita¹, Masashi Kurosawa¹, Osamu Nakatsuka^1,2, Shigehisa Shibayama¹ (1.Nagoya Univ., 2.IMaSS, Nagoya Univ.)

11:30 AM - 11:45 AM

[17a-A403-10] Possible Use of Band-to-Band Tunneling in Soft-Error Reliability Prediction

〇(M2)Yoshitaka Kato^1,2, Daisuke Kobayashi², Kazuyuki Hirose^1,2 (1.UTokyo, 2.ISAS)

Sessions

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[16a-A403-1~10] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

△ [16a-A403-2] Characterization of Charge Noise in an nMOS Si Quantum Dot using RF Reflectometry

△ [16a-A403-4] Design and evaluation of single-stage matching circuits suitable for RF reflectometry of a physically defined quantum dot

[16p-A403-1~20] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

▲ [16p-A403-6] 3D NAND Memory Operation of Oxide-Semiconductor Channel FeFETs

▼ [16p-A403-8] A Simulation Study on Memory Characteristics of Oxide-Semiconductor Channel Antiferroelectric FETs Using Half-Loop Hysteresis

▲ [16p-A403-14] Tuning of Conductance Values by Si Doping in GeTe for Artificial Synapse Characteristics

△ [16p-A403-16] Interfacial Analysis of Low Temperature Deposited CVD-SiO2 for Direct Bonding

△ [16p-A403-17] Kinetics of Dangling Bonds and Open Spaces of SiCN for Surface for Plasma Activated Direct Bonding

▲ [16p-A403-18] Effects of Annealing on Thermal Boundary Resistance of Low-k Interlayer Dielectrics

▲ [16p-A403-20] Cu diffusion barrier property evaluation of 1-nm-thick PVD-Co(W) films by time-lag method

[17a-A403-1~10] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

▲ [17a-A403-4] Self-heating and Short-Channel Effect Immunity with Partial-Bottom-Dielectric-Isolation for Gate-All-Around Nano-Sheet FETs

Authenticate

△ [16p-A403-16] Interfacial Analysis of Low Temperature Deposited CVD-SiO₂ for Direct Bonding