[16p-A403-1~20] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

▲ [16p-A403-6] 3D NAND Memory Operation of Oxide-Semiconductor Channel FeFETs

〇(M2)Junxiang Hao¹, Xiaoran Mei¹, Takuya Saraya¹, Toshiro Hiramoto¹, Masaharu Kobayashi^1,2 (1.IIS, Univ. of Tokyo, 2.d.lab, Univ. of Tokyo)

Keywords:FeFET, Oxide Semiconductor, 3D NAND

We have explored 3D NAND memory operation of oxide-semiconductor (OS) channel FeFETs by
TCAD simulation with a multi-transistor NAND string model. Key challenges in 3D NAND memory
devices, such as (1) pass voltage disturb, (2) interference from adjacent cells, and (3) inhibit operation of unselected bitlines, are addressed. For a target device structure, operation voltages can be optimized to satisfy the requirement of (1)-(3). This paper will provide insights on the feasibility of 3D NAND FeFETs for high capacity storage memory.