The 63rd JSAP Spring Meeting, 2016

Presentation information

Oral presentation

13 Semiconductors » 13.4 Si wafer processing /Si based thin film /MEMS/Integration technology

[20p-S423-1~19] 13.4 Si wafer processing /Si based thin film /MEMS/Integration technology

Sun. Mar 20, 2016 1:45 PM - 6:45 PM S423 (S4)

Seiichiro Higashi(Hiroshima Univ.), Akito Hara(Tohoku Gakuin Univ.)

2:15 PM - 2:30 PM

[20p-S423-3] Self-Aligned Planar Metal Double Gate Low-Temperature thin Poly-Ge TFTs on a Glass Substrate

Yuya Nishimura1, Takuya Nakashima1, Makoto Mori1, Akito Hara1 (1.Tohoku Gakuin Univ.)

Keywords:semiconductor,TFT,Ge

Self-aligned planar metal double-gate (DG) low-temperature (LT) poly-Ge TFTs was fabricated on glass substrate, in which channel poly-Ge thickness was 15 nm. It was observed that on/off ratio of this TFT is six times larger than that of top gate LT poly-Ge TFTs with same channel thickness. Moreover, low voltage operation of DG LT poly-Ge TFT, compared to that of TG LT poly-Ge TFT, was confirmed. It is attractive that maximum TFT fabrication process temperature in this experiment is 300C, except for crystallization process. Thus, this TFT fabrication process is applicable for not only glass substrate but also plastic substrate.