Oral presentation

[20a-CE-1~12] 13.5 Semiconductor devices and related technologies

Thu. Sep 20, 2018 9:00 AM - 12:15 PM CE (Century Hall)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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9:00 AM - 9:15 AM

[20a-CE-1] Physical Modeling for Fluctuation of Grain-Boundary Resistance in Polycrystalline Silicon

〇Michiru Hogyoku¹, Takashi Izumida¹, Hiroyoshi Tanimoto¹, Nobutoshi Aoki¹, Seiji Onoue¹ (1.Toshiba Memory Corp.)

9:15 AM - 9:30 AM

▼ [20a-CE-2] Reduced Subthreshold Slope Variability at High Temperature in Bulk and SOTB MOSFETs

〇(M2)Shuang Gao¹, Tomoko Mizutani¹, Kiyoshi Takeuchi¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (1.IIS, Univ. of Tokyo)

9:30 AM - 9:45 AM

▲ [20a-CE-3] Reduced Drain-Induced-Barrier-Lowering (DIBL) Variability at High Temperature in Bulk and SOTB MOSFETs

〇(M2)Shuang Gao¹, Tomoko Mizutani¹, Kiyoshi Takeuchi¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (1.IIS, Univ. of Tokyo)

9:45 AM - 10:00 AM

[20a-CE-4] Application of post-fabrication cell stability self-improvement using multiple stress technique to bulk SRAM cell array

〇Tomoko Mizutani¹, Kiyoshi Takeuchi¹, Takuya Saraya¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (1.IIS, Univ. of Tokyo)

10:00 AM - 10:15 AM

[20a-CE-5] Design and analysis of virtually nonvolatile retention Flip-Flop using dual-mode inverters

〇Daiki Kitagata¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.Tokyo Inst. of Tech.)

10:15 AM - 10:30 AM

[20a-CE-6] Design and analysis of virtually nonvolatile retention SRAM using dual-mode inverters

〇Hayato Yoshida¹, Daiki Kitagata¹, Shuu'ichiro Yamamoto¹, Satoshi Sugahara¹ (1.FIRST,Tokyo inst. of Tech.)

10:45 AM - 11:00 AM

[20a-CE-7] Parasitic resistance characterization of FinFETs doped by solid-diffusion of phosphorus

〇Takashi Matsukawa¹, Takahiro Mori¹, Yoshihiro Sawada², Yohei Kinoshita², Yongxun Liu¹, Meishoku Masahara¹ (1.AIST, 2.Tokyo Ohka Kogyo)

11:00 AM - 11:15 AM

△ [20a-CE-8] Improvement of electrostatic gate-controlling for InAs nanowire vertical SGTs on Si

〇(M1)Hironori Gamo¹, Katsuhiro Tomioka¹, Junichi Motohisa¹ (1.Graduate School of IST and RCIQE, Hkkaido Univ.)

11:15 AM - 11:30 AM

[20a-CE-9] Sensitivity Characteristics of GaAsSb/InAs Nanowire Backward Diodes at 2.4 GHz

〇Tsuyoshi Takahashi^1,2, Kenichi Kawaguchi^1,2, Masaru Sato^1,2, Naoya Okamoto^1,2, Michihiko Suhara³ (1.Fujitsu, 2.Fujitsu Labs., 3.Tokyo Metro. Univ.)

11:30 AM - 11:45 AM

[20a-CE-10] Hole mobility enhancement in Ultra-smooth UTB-GeOI

〇WENHSIN CHANG¹, Toshifumi Irisawa¹, Hiroyuki Ishii¹, Noriyuki Uchida¹, Tatsuro Maeda¹ (1.AIST)

11:45 AM - 12:00 PM

▼ [20a-CE-11] Impact of SiGe Layer Thickness in Starting Substrates on Properties of Ultrathin Body Ge-on-insulator pMOSFETs fabricated by Ge Condensation

〇(DC)KwangWon Jo¹, WuKang Kim¹, Mitsuru Takenaka¹, Takagi Shinichi¹ (1.The university of Tokyo)

12:00 PM - 12:15 PM

[20a-CE-12] Demonstration of Ultralow (<10^-20 A/um) Off Leakage Current In-Zn-O Channel Transistor with EOT of 6.2nm

〇Nobuyoshi Saito¹, Tomoaki Sawabe¹, Junji Kataoka¹, Ueda Tomomasa¹, Tezuka Tsutomu¹, Ikeda Keiji¹ (1.Toshiba Memory Corp.)

Oral presentation

[21a-CE-1~10] 13.5 Semiconductor devices and related technologies

Fri. Sep 21, 2018 9:00 AM - 11:30 AM CE (Century Hall)

Hiroyuki Ota(AIST)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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9:00 AM - 9:15 AM

△ [21a-CE-1] Effects of Dopants on Tunneling Current at Si-p/n Junction;Theoretical Study

〇(M1)Sanghun Cho¹, Shota Iizuka², Takashi Nakayama¹ (1.Chiba Univ., 2.NIMS)

9:15 AM - 9:30 AM

[21a-CE-2] Super Steep Switching in TFET Having Trimmed Gate Structure

〇Hidehiro Asai¹, Takahiro Mori¹, Takashi Matsukawa¹, Junichi Hattori¹, Kazuhiko Endo¹, Koichi Fukuda¹ (1.AIST)

9:30 AM - 9:45 AM

[21a-CE-3] Influences of channel thickness fluctuation on electrical properties of bilayer tunneling field effect transistors

〇Kimihiko Kato¹, Hiroaki Matsui¹, Hitoshi Tabata¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.Univ. of Tokyo)

9:45 AM - 10:00 AM

△ [21a-CE-4] Planar-type InGaAs TFET with sub-60mV/dec S.S. by gate stack engineering of ZrO2

〇(DC)DAEHWAN AHN¹, Sang-Hee Yoon¹, Kimihiko Kato¹, Taichiro Fukui¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.Tokyo Univ.)

10:00 AM - 10:15 AM

[21a-CE-5] Effect of Substrate Bias on P/N-Channel Super-Steep SS PN-Body-Tied SOI-FET

〇(M1)Wataru Yabuki¹, Jiro Ida¹, Takayuki Mori¹, Hiroki Endo¹, Syunichi Nakano¹ (1.kanazawa inst of tec.)

10:15 AM - 10:30 AM

[21a-CE-6] Transient characterization with pulse measurement on Super Steep SS PN-Body Tied SOI FET

〇(M1)Hiroki Endo¹, Jiro Ida¹, Takayuki Mori¹, Shunichi Nakano¹, Wataru Yabuki¹ (1.Kanazawa Inst of Tech.)

10:30 AM - 10:45 AM

▼ [21a-CE-7] Steep Subthreshold Slope in Ferroelectric FET by Transient Negative Capacitance Effect with Polarization Switching Delay

〇(D)Chengji Jin¹, Takuya Saraya¹, Toshiro Hiramoto¹, Masaharu Kobayashi¹ (1.IIS, Univ. of Tokyo)

10:45 AM - 11:00 AM

[21a-CE-8] Design methodology of a new piezoelectronic transistor

〇Yusaku Shiotsu¹, Shuu'ichiro Yamamoto¹, Hiroshi Funakubo², Minoru Kuribayashi Kurosawa³, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech., 2.Dept. of Mater. Sci. and Eng., Tokyo Inst. of Tech., 3.Dept. of Electr. and Electron. Eng., Tokyo Inst. of Tech.)

11:00 AM - 11:15 AM

△ [21a-CE-9] Radio-frequency reflectometry on an undoped Si quantum dot

〇Mizuki Kobayashi¹, Egle Tylaite¹, Yu Yamaoka¹, Tetsuo Kodera¹ (1.Tokyo Tech)

11:15 AM - 11:30 AM

[21a-CE-10] Magnetic field direction dependence of hole spin transport in silicon quantum dots

〇Kou Amano¹, Mizuki Kobayashi¹, Seiya Mizoguchi¹, Yu Ymaoka¹, Kazuma Iwasaki¹, Tetsuo Kodera¹ (1.Tokyo Tech.)

Poster presentation

[21p-PB3-1~5] 13.5 Semiconductor devices and related technologies

Fri. Sep 21, 2018 1:30 PM - 3:30 PM PB (Shirotori Hall)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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1:30 PM - 3:30 PM

[21p-PB3-1] Short Channel Effects and Surface Potential of Tunnel FET’s

〇Koichi Fukuda¹, Hidehiro Asai¹, Junichi Hattori¹, Takahiro Mori¹, Yukinori Morita¹, Wataru Mizubayashi¹, Meishoku Masahara¹, Shinji Migita¹, Hiroyuki Ota¹, Kazuhiko Endo¹, Takashi Matsukawa¹ (1.AIST)

1:30 PM - 3:30 PM

[21p-PB3-2] Multi layered metal nanoparticles embedded V-groove Junctionless-FET

〇Takahiko Ban¹, Shinji Migita², Mutsunori Uenuma³, Yasuaki Ishikawa³, Ichiro Yamashita³, Yukiharu Uraoka³, Shin-ichi Yamamoto¹ (1.Ryukoku Univ., 2.AIST, 3.NAIST)

1:30 PM - 3:30 PM

[21p-PB3-3] Improving performance of CBRAM introducing Metal-Organic Framework films

〇Kohei Yamashita¹, Takuya Nakamichi¹, Sang-Seok Lee¹, Satoru Kishida¹, Kentaro Kinoshita² (1.Tottori Univ., 2.Tokyo Univ. of Science)

1:30 PM - 3:30 PM

▼ [21p-PB3-4] Role of Traps in Few Layer n-ReS₂ Phototransistor on top of p-MoTe₂ Layer

〇(P)Bablu Mukherjee¹, Mohd Amir Zulkefli¹, Keiji Ueno², Yutaka Wakayama¹, Shu Nakaharai¹ (1.Natl. Inst. For Materials Science, 2.Saitama University)

1:30 PM - 3:30 PM

▼ [21p-PB3-5] Charge Trapping and Hysteresis Behavior in ReS₂/SiO₂ and ReS₂/hBN
Field Effect Transistors

〇(D)Amir Zulkefli^1,2, Bablu Mukherjee¹, Kenji Watanabe¹, Takashi Taniguchi¹, Yutaka Wakayama^1,2, Shu Nakaharai¹ (1.National Inst. for Materials Science, 2.Kyushu Univ.)

Sessions

13 Semiconductors » 13.5 Semiconductor devices and related technologies

[20a-CE-1~12] 13.5 Semiconductor devices and related technologies

[20a-CE-1] Physical Modeling for Fluctuation of Grain-Boundary Resistance in Polycrystalline Silicon

▼ [20a-CE-2] Reduced Subthreshold Slope Variability at High Temperature in Bulk and SOTB MOSFETs

▲ [20a-CE-3] Reduced Drain-Induced-Barrier-Lowering (DIBL) Variability at High Temperature in Bulk and SOTB MOSFETs

[20a-CE-4] Application of post-fabrication cell stability self-improvement using multiple stress technique to bulk SRAM cell array

[20a-CE-5] Design and analysis of virtually nonvolatile retention Flip-Flop using dual-mode inverters

[20a-CE-6] Design and analysis of virtually nonvolatile retention SRAM using dual-mode inverters

[20a-CE-7] Parasitic resistance characterization of FinFETs doped by solid-diffusion of phosphorus

△ [20a-CE-8] Improvement of electrostatic gate-controlling for InAs nanowire vertical SGTs on Si

[20a-CE-9] Sensitivity Characteristics of GaAsSb/InAs Nanowire Backward Diodes at 2.4 GHz

[20a-CE-10] Hole mobility enhancement in Ultra-smooth UTB-GeOI

▼ [20a-CE-11] Impact of SiGe Layer Thickness in Starting Substrates on Properties of Ultrathin Body Ge-on-insulator pMOSFETs fabricated by Ge Condensation

[20a-CE-12] Demonstration of Ultralow (<10^-20 A/um) Off Leakage Current In-Zn-O Channel Transistor with EOT of 6.2nm

[21a-CE-1~10] 13.5 Semiconductor devices and related technologies

△ [21a-CE-1] Effects of Dopants on Tunneling Current at Si-p/n Junction;Theoretical Study

[21a-CE-2] Super Steep Switching in TFET Having Trimmed Gate Structure

[21a-CE-3] Influences of channel thickness fluctuation on electrical properties of bilayer tunneling field effect transistors

△ [21a-CE-4] Planar-type InGaAs TFET with sub-60mV/dec S.S. by gate stack engineering of ZrO2

[21a-CE-5] Effect of Substrate Bias on P/N-Channel Super-Steep SS PN-Body-Tied SOI-FET

[21a-CE-6] Transient characterization with pulse measurement on Super Steep SS PN-Body Tied SOI FET

▼ [21a-CE-7] Steep Subthreshold Slope in Ferroelectric FET by Transient Negative Capacitance Effect with Polarization Switching Delay

[21a-CE-8] Design methodology of a new piezoelectronic transistor

△ [21a-CE-9] Radio-frequency reflectometry on an undoped Si quantum dot

[21a-CE-10] Magnetic field direction dependence of hole spin transport in silicon quantum dots

[21p-PB3-1~5] 13.5 Semiconductor devices and related technologies

[21p-PB3-1] Short Channel Effects and Surface Potential of Tunnel FET’s

[21p-PB3-2] Multi layered metal nanoparticles embedded V-groove Junctionless-FET

[21p-PB3-3] Improving performance of CBRAM introducing Metal-Organic Framework films

▼ [21p-PB3-4] Role of Traps in Few Layer n-ReS₂ Phototransistor on top of p-MoTe₂ Layer

▼ [21p-PB3-5] Charge Trapping and Hysteresis Behavior in ReS₂/SiO₂ and ReS₂/hBN
Field Effect Transistors

Authentication

Sessions

13 Semiconductors » 13.5 Semiconductor devices and related technologies

[20a-CE-1~12] 13.5 Semiconductor devices and related technologies

▼ [20a-CE-2] Reduced Subthreshold Slope Variability at High Temperature in Bulk and SOTB MOSFETs

▲ [20a-CE-3] Reduced Drain-Induced-Barrier-Lowering (DIBL) Variability at High Temperature in Bulk and SOTB MOSFETs

△ [20a-CE-8] Improvement of electrostatic gate-controlling for InAs nanowire vertical SGTs on Si

▼ [20a-CE-11] Impact of SiGe Layer Thickness in Starting Substrates on Properties of Ultrathin Body Ge-on-insulator pMOSFETs fabricated by Ge Condensation

[21a-CE-1~10] 13.5 Semiconductor devices and related technologies

△ [21a-CE-1] Effects of Dopants on Tunneling Current at Si-p/n Junction;Theoretical Study

△ [21a-CE-4] Planar-type InGaAs TFET with sub-60mV/dec S.S. by gate stack engineering of ZrO2

▼ [21a-CE-7] Steep Subthreshold Slope in Ferroelectric FET by Transient Negative Capacitance Effect with Polarization Switching Delay

△ [21a-CE-9] Radio-frequency reflectometry on an undoped Si quantum dot

[21p-PB3-1~5] 13.5 Semiconductor devices and related technologies

▼ [21p-PB3-4] Role of Traps in Few Layer n-ReS2 Phototransistor on top of p-MoTe2 Layer

▼ [21p-PB3-5] Charge Trapping and Hysteresis Behavior in ReS2/SiO2 and ReS2/hBNField Effect Transistors

Authentication

▼ [21p-PB3-4] Role of Traps in Few Layer n-ReS₂ Phototransistor on top of p-MoTe₂ Layer

▼ [21p-PB3-5] Charge Trapping and Hysteresis Behavior in ReS₂/SiO₂ and ReS₂/hBN
Field Effect Transistors