[P-1] Japanese Management in an Era of Change

Jiro Ushio (1.Ushio Inc.)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード

[P-2] Interconnect Limits on Gigascale Integration

James D. Meindl

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード

[P-3] R&D Challenges and Chance in Today's Japan

Seiki Ogura (1.Halo LSI Design and Device Technology Inc.)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード

[A-1-1] Effects of the Scaling on n+/p Junction Leakage Characteristics

T. Fukai、K. Takeuchi、T. Mogami (1.ULSI Research Lab., Silicon Systems Research Labs., NEC)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード

[A-1-2] Leakage Mechanism of Local Junctions Forming Main or Tail Mode of DRAM Retention Characteristics

Shuichi Ueno、Yasuo Inoue、Masahide Inuishi (1.ULSI development center, MITSUBISHI electric corporation)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード

[A-1-3] Characteristics of Dual Polymetal (W/WNx/Poly-Si) Gate CMOS for 0.1 μm DRAM Technology

Yong-Hae Kim、Sung-Keun Chang、Seon-Soon Kim、Jun-Gi Choi、Sang-Hee Lee Dae-Hee Hahn、Hyung-Duck Kim (1.Semiconductor Advanced Research Division, Hyundai Electronics Industries)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード

[A-1-4] A New Observation of the Width Dependent Hot Carrier Effect in Shallow-Trench-Isolated P-MOSFET's

Steve S. Chung、W.-J. Yang、C.-M. Yih、J.-J. Yang (1.Department of Electronic Engineering, National Chiao Tung University、2.Worldwide Semiconductor Manufacturing Co.)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード

[A-1-5] Stress Induced Subthreshold Current Hump in Short Gate-Length pMOSFET's with Shallow Trench Isolation

L. P. Chiang、L. Y. Huang、N. K. Zous、Tahui Wang (1.Department of Electronics Engineering, National Chiao-Tung University)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード

[A-1-6] Optimized Shallow Trench Isolation Technology for DRAM Embedded Logic Process

T. Yamazaki、K. Ohno、N. Tsuchiya、T. Gocho (1.Process Development Department, LSI R&D Group, Core Technology & Network Company, Sony Corp.)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード

[A-2-1] Transport Properties in Sub-10-nm-gate EJ-MOSFETs

Hisao Kawaura、Toshitsugu Sakamoto、Toshio Baba (1.Fundamental Research Laboratories, NEC Corporation)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード