[PS-4-09] Impacts of Low Temperature formed SiO₂ Tunneling and Si₃N₄/HfO₂ Trapping Layers on Gate-All-Around Charge-Trapping Flash Memory Devices

^○P. -Y. Lin¹, K. -S. Chang-Liao¹, H. -K. Fang¹, C. -H. Cheng¹, W. -H. Huang², C. -H. Shen², J. -M. Shieh² (1.National Tsing Hua Univ. (Taiwan), 2.National Nano Device Labs. (Taiwan))

2017 International Conference on Solid State Devices and Materials |PDF Download

[PS-4-10] New Tunnel FET Charge-Trapping Memory with Large Memory Window for Ultra Low Power Operation

^○H. Kino¹, T. Fukushima¹, T. Tanaka¹ (1.Tohoku Univ. (Japan))

2017 International Conference on Solid State Devices and Materials |PDF Download

[PS-4-11] V_th variation of string SONOS NAND Flash depending on single grain boundary and stored electron charges in an adjacent cell

^○H. Oh¹, J. Kim¹, R. -H. Baek¹, J. -S. Lee¹ (1.POSTECH (Korea))

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[PS-4-12] Poly-Ge Tri-gate Nanowire Junctionless Charge-Trapping Flash Devices Formed with Low-Temperature Processes for 3D Memory Applications

^○Y. -C. Lu¹, K. -S. Chang-Liao¹, H. -K. Fang¹, K. -Y. Li¹, W. -H. Huang², C. -H. Shen², J. -M. Shieh² (1.National Tsing Hua Univ. (Taiwan), 2.National Nano Device Labs. (Taiwan))

2017 International Conference on Solid State Devices and Materials |PDF Download

[PS-4-13] Spin orbit torque magnetization switching of a tungsten based three terminal perpendicular magnetic tunnel junction for low power Spin Orbit Torque MRAM application

^○Y. Guerfi¹, T. Brächer², O. Boulle², J. Langer³, B. Ocker³, P. Gambardella⁴, M. -C. Cyrille¹, G. Gaudin² (1.CEA-Leti (France), 2.Univ. Grenoble Alpes, CNRS, CEA, Grenoble INP, INAC, SPINTEC (France), 3.Singulus Tech. (Germany), 4.ETH Zurich (Switzerland))

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[PS-4-14] Investigation of bias polarity dependence on set operation in phase change memory using GeCu₂Te₃

^○J. An¹, K. Kim¹, C. Choi¹, S. Shindo², Y. Sutou², Y. Song¹ (1.Hanyang Univ. (Korea), 2.Tohoku Univ. (Japan))

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[PS-4-15 (Late News)] Strain-Enhanced Ferroelectric Aluminum-Doped Hafnium Oxides for Volatile and Nonvolatile Memories Applications

^○C. Liu¹, C. -C. Fan¹, Y. -R. Chen¹, G. -L. Liou², Y. -C. Chiu¹, C. -Y. Chang², C. -H. Cheng¹, H. -H. Hsu³ (1.National Chiao Tung Univ. (Taiwan), 2.National Taiwan Normal Univ. (Taiwan), 3.National Taipei Univ. of Tech. (Taiwan))

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[PS-5-01] Octagonal MOSFET for Simultaneous Sensing of Temperature and Magnetic Field

^○T. Harada¹, K. Kaiwa¹ (1.Yamagata Univ. (Japan))

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[PS-5-02] Sensor assembly method using Si-interposer with trenches for 3-D binocular range sensors

^○K. Nakajima¹ (1.Kyushu Inst. of Tech. (Japan))

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[PS-5-03] Temperature Sensors with Negative and Positive Temperature Coefficients by Using Cascoded Diode-connected Sub-threshold NMOSFETs and PMOSFETs

R. -L. Wang¹,^○K. -B. Lee¹, C. -S. Tsai¹, L. -W. Wang¹, Y. -Y. Lin¹, H. -Y. Chen¹, Y. -T. Chuang², H. -H. Liao², H. -H. Tsai², Y. -Z. Juang² (1.National Kaohsiung Normal Univ. (Taiwan), 2.National Applied Research Lab., National Chip Implementation Center (Taiwan))

2017 International Conference on Solid State Devices and Materials |PDF Download