[15a-B410-1~9] 13.4 Si processing /Si based thin film / MEMS / Equipment technology

[15a-B410-3] Investigation of Shrinkage of Overlap Length of SOI CMOS of Minimal Fab

〇Takeshi Hamamoto¹, Yuji Kitayama³, Satoshi Maruyama³, Sommawan Khumpuang^1,2, Yasunari Shiba³, Shiro Hara^1,2,4 (1.MINIMAL, 2.AIST, 3.Yokogawa Solution, 4.Hundred)

Keywords:SOI, MOSFET

Minimal fab is a production system that targets high-mix low-volume production. As a result of device application in this minimal fab, MEMS devices represented by cantilever, CMOS, Ring Oscillator and operational amplifier using it have been prototyped. The operation verification of the 1,000Gate level integrated circuit has already been completed, and it has been put into practical use as a prototype fab. In the future, we will create a PDK (Process Design Kit) and focus on improving the operation accuracy of MOSFETs and ensuring process robustness in order to support circuit operations based on a wide range of user designs. This time, we report the result of the study on the reduction of the overlap length as part of the size reduction of the MOSFET.