Oral presentation

13. Semiconductors A (Silicon) » 13.4 Devices/Integration Technologies

[18p-A16-1~14] 13.4 Devices/Integration Technologies

Thu. Sep 18, 2014 1:30 PM - 5:15 PM A16 (E307)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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Lunch 12:00～13:30 (12:00 PM - 1:30 PM)

1:30 PM - 1:45 PM

[18p-A16-1] Time-Domain Multiply-and-Accumulation with a FinFET and nanodisk array structures

^○Yoshiaki Kuramitsu¹, Takashi Tohara¹, Kazuhiko Endo², Seiji Samukawa³, Meishoku Masahara², Takashi Morie¹ (Kyushu Inst.¹, AIST², Tohoku Univ.³)

1:45 PM - 2:00 PM

△ [18p-A16-2] A process technique for combining a FinFET and nanodisk array structures

^○Takashi Tohara¹, Kazuhiko Endo², Yongxun Liu², Makoto Igarashi³, Seiji Samukawa³, Meishoku Masahara², Takashi Morie¹ (Kyushu Inst.¹, AIST², Tohoku Univ.³)

2:00 PM - 2:15 PM

[18p-A16-3] A scaling limit of MOSFETs associated with drain electrode

^○Kenji Natori¹ (Tokyo Tech.¹)

2:15 PM - 2:30 PM

[18p-A16-4] Operation Limit Imposed by Potential Fluctuations due to Random Dopant in JL-FETs

^○(M1)Kazusa Inoue¹, Katsuhisa Yoshida¹, Nobuyuki Sano¹ (Univ. of Tsukuba¹)

2:30 PM - 2:45 PM

[18p-A16-5] Implementation of Self-Image Potential into Nano-Device Simulations

^○(M1)Yosuke Tsuchiya¹, Katsuhisa Yoshida¹, Nobuyuki Sano¹ (Inst. Appl. Phys, Univ.of Tsukuba¹)

2:45 PM - 3:00 PM

[18p-A16-6] Analytic Compact Model of Source-Drain Tunneling Current in Cylindrical Gate-All-Around MOSFET

^○He Cheng^1,3, Shigeyasu Uno^2,3, Kazuo Nakazato¹ (Naogya Univ.¹, Ritsumeikan Univ.², JST CREST³)

3:00 PM - 3:15 PM

△ [18p-A16-7] Atomistic Calculation of Phonon-limited Hole Mobility in Rectangular Cross-sectional Ge Nanowires

^○Hajime Tanaka¹, Seigo Mori¹, Naoya Morioka¹, Jun Suda¹, Tsunenobu Kimoto¹ (Kyoto Univ.¹)

Break 15:15～15:30 (3:15 PM - 3:30 PM)

3:30 PM - 3:45 PM

[18p-A16-8] Experimental Study on 2D-Si Layers for Future Several-nm CMOS(Ⅷ)

^○Yuya Suzuki¹, Yoshiki Nagamine¹, Masahiro Yamanaka¹, Takashi Aoki¹, Tomohisa Mizuno¹, Tatsurou Maeda² (Kanagawadaigaku¹, Sansouken²)

3:45 PM - 4:00 PM

[18p-A16-9] Experimental Study on 2D-Si Layers for Future Several-nm CMOS (IX)

tomohisa mizuno¹, takashi aoki¹, yuuya suzuki¹, ^○yoshiki nagamine¹, toshiyuki samezima² (Kanagawa Univ¹, Toukyounoukou Univ²)

4:00 PM - 4:15 PM

△ [18p-A16-10] Impacts of Orientation and Cross-sectional Shape on Hole Mobility of Si Nanowire MOSFETs

^○Hiroaki Fujihara¹, Naoya Morioka¹, Hajime Tanaka¹, Jun Suda¹, Tsunenobu Kimoto¹ (Kyoto Univ.¹)

4:15 PM - 4:30 PM

▼ [18p-A16-11] Effects of thinning condensation UTB GOI films by additional thermal oxidation on GOI Characteristics

^○WuKang Kim^1,2, Shinichi Takagi^1,2, Mitsuru Takenaka^1,2 (The University of Tokyo¹, JST-CREST²)

4:30 PM - 4:45 PM

[18p-A16-12] Large-scale Ultrathin Ge-on-Insulator wafer Using Epitaxial Lift-Off (ELO) Technique

^○Tatsuro Maeda¹, Eiko Mieda¹, Hiroyuki Ishii¹, Hiroyuku Hattori¹, Taro Itatani¹, Tetsuji Yasuda¹, Yuuichi Kurashima¹, Hideki Takagi¹, Takeshi Aoki², Yugami Jiro³, Taketsugu Yamamoto², Osamu Ichikawa², Takenori Osada², Tomoyuki Takada², Masahiko Hata², Arito Ogawa³, Toshiyuki Kikuchi³, Yasuo Kunii³ (AIST¹, Sumitomo Chemical², Hitachi Kokusai Electric³)

4:45 PM - 5:00 PM

[18p-A16-13] Formation and Electrical Characteristics of MoS₂ Film by High-Temperature Sputtering

^○Kentarou Matsuura¹, Takumi Ohashi¹, Shimpei Yamaguchi¹, Kouhei Suda², Seiya Ishihara², Naomi Sawamoto², Kuniyuki Kakushima¹, Nobuyuki Sugii¹, Akira Nishiyama¹, Yoshinori Kataoka¹, Kenji Natori¹, Kazuo Tsutsui¹, Hiroshi Iwai¹, Atsushi Ogura², Hitoshi Wakabayahi¹ (Tokyo Tech.¹, Meiji Univ.²)

5:00 PM - 5:15 PM

[18p-A16-14] MoS₂ Film Thinning and Electrical Characteristics on High-Temperature Sputtering

^○Takumi Ohashi¹, Shimpei Yamaguchi¹, Kentarou Matsuura¹, Kohei Suda², Seiya Ishihara², Naomi Sawamoto², Kuniyuki Kakushima¹, Nobuyuki Sugii¹, Akira Nishiyama¹, Yoshinori Kataoka¹, Kenji Natori¹, Kazuo Tsutsui¹, Hiroshi Iwai¹, Atsushi Ogura², Hitoshi Wakabayahi¹ (Tokyo Tech.¹, Meiji Univ.²)