Poster presentation

[18p-PA12-1~10] 13.4 Devices/Integration Technologies

Tue. Mar 18, 2014 4:00 PM - 6:00 PM PA12 (アリーナ)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

+Add all to schedule

4:00 PM - 6:00 PM

[18p-PA12-1] Evaluation of Electron Transport Property at 4 K for Long Channel Transistor with a One-Dimensional Phosphorus Dopant Array

^○Kuninori Kumagai¹, Enrico Prati², Masahiro Hori³, Yuiko Fukui¹, Takashi Tanii¹, Takahiro Shinada⁴ (Waseda Univ.¹, CNR-IFN², Univ. of Toyama³, AIST⁴)

4:00 PM - 6:00 PM

[18p-PA12-2] Mechanisms of hole mobility enhancement in (100) pMOSFET on Si substrates

^○Yuji Asakura^1,2, Koji Araki³, Moriya Miyashita³, Koji Izunome³, Mitsuru Takenaka^1,2, Shinichi Takagi^1,2 (The University of Tokyo¹, JST CREST², GlobalWafers Japan³)

4:00 PM - 6:00 PM

[18p-PA12-3] Analysis of Transistor Characteristics in Distribution Tails beyond ±5.4σ of 11 Billion Transistors

^○Tomoko Mizutani¹, Anil Kumar¹, Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹)

4:00 PM - 6:00 PM

[18p-PA12-4] Advantage of (100)/<100> Oriented Channels in Biaxially- and Uniaxially Strained-Ge-On-Insulator pMOSFETs with NiGe Metal Source/Drain

^○Keiji Ikeda¹, Yoshihiko Moriyama¹, Yuuichi Kamimuta¹, Mizuki Ono¹, Toshifumi Irisawa¹, Minoru Oda¹, Etsuo Kurosawa¹, Tsutomu Tezuka¹ (GNC-AIST¹)

4:00 PM - 6:00 PM

△ [18p-PA12-5] Ultra-thin body Ge-on insulator nMOSFETs by Ge condensation and Sb-diffused source/drain

^○WuKang Kim^{1, 2}, YoungHyun Kim^{1, 2}, SangHyeon Kim^{1, 2}, Takenori Osada³, MAsahiko Hata³, Mitsuru Takenaka^{1, 2}, Shinichi Takagi^{1, 2} (The University of Tokyo¹, JST-CREST², Sumitomo Chemical³)

4:00 PM - 6:00 PM

[18p-PA12-6] Triangular InGaAs-OI nMOSFET with high mobility (111)B surfaces

^○Toshifumi Irisawa¹, Minoru Oda¹, Keiji Ikeda¹, Yoshihiko Moriyama¹, Eiko Mieda¹, Jevaswan Wipakorn¹, Tatsurou Maeda¹, Osamu Ichikawa², Takenori Osada², Yasuyuki Miyamoto³, Masahiko Hata², Tsutomu Tezuka¹ (AIST-GNC¹, Sumitomo Cemical Co. Ltd², T.I.Tech.³)

4:00 PM - 6:00 PM

[18p-PA12-7] Low-dielectric constant SiCN charge trapping layer for nonvolatile memory applications(Ⅲ)

^○（B）Yoshina Ito¹, Shinji Naito², Kiyoteru Kobayashi^1,2 (Tokai Univ.¹, Tokai Univ.²)

4:00 PM - 6:00 PM

[18p-PA12-8] Low-dielectric constant SiCN charge trapping layer for nonvolatile memory applications(Ⅳ)

^○（M1）Shinji Naito¹, Yoshina Ito², Kiyoteru Kobayashi^1,2 (Tokai Univ.¹, Tokai Univ.²)

4:00 PM - 6:00 PM

[18p-PA12-9] Proposal of Super Steep Subthreshold Slope with PN Body-Contacted SOI MOSFET at Ultra Low Drain Voltage

^○Takayuki Mori¹, Sou Tashino¹, Jiro Ida¹ (Kanazawa Inst. of Tech.¹)

4:00 PM - 6:00 PM

[18p-PA12-10] CMOS Track-and-Hold Circuit for Sampling Gaussian Monocycle Pulse

^○Yuji Seo¹, Kenta Sogo¹, Akihiro Toya², Takamaro Kikkawa¹ (Research Institute for Nanodevice and Bio Systems, Hiroshima Univ.¹, Kure National College of Technology²)

Oral presentation

[19a-F12-1~13] 13.4 Devices/Integration Technologies

Wed. Mar 19, 2014 9:00 AM - 12:30 PM F12 (F408)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

+Add all to schedule

9:00 AM - 9:15 AM

[19a-F12-1] Channel Size Dependence of Low-Frequency Noise in Si Tri-gate Nanowire Transistors

^○Masumi Saitoh¹, Kensuke Ota¹, Chika Tanaka¹, Toshinori Numata¹ (Toshiba Corp.¹)

9:15 AM - 9:30 AM

△ [19a-F12-2] Evaluation of Self-Heating Effects in Nanoscale Bulk and Ultra-Thin BOX SOI MOSFETs Using Four-Terminal Gate Resistance Technique

^○（P）Tsunaki Takahashi¹, Takeo Matsuki³, Takahiro Shinada^2,3, Yasuo Inoue³, Ken Uchida¹ (Dept. Electrical and Electronics Eng., Keio Univ.¹, Nanoelectronics RI, AIST², TIA Headquaters, AIST³)

9:30 AM - 9:45 AM

[19a-F12-3] Analysis of FinFET variability caused by granular work function variation of metal gates

^○Takashi Matsukawa¹, Kouichi Fukuda¹, Yongxun Liu¹, Kazuhiko Endo¹, Junichi Tsukada¹, Hiromi Yamauchi¹, Yuki Ishikawa¹, Shinichi O'uchi¹, Wataru Mizubayashi¹, Hiroyuki Ota¹, Shinji Migita¹, Yukinori Morita¹, Meishoku Masahara¹ (AIST, NeRI¹)

9:45 AM - 10:00 AM

[19a-F12-4] Reduced Minimum Operation Voltage in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells

^○Tomoko Mizutani¹, Yoshiki Yamamoto², Hideki Makiyama², Hirofumi Shinohara², Toshiaki Iwamatsu², Hidekazu Oda², Nobuyuki Sugii², Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, LEAP²)

10:00 AM - 10:15 AM

[19a-F12-5] Statistical Characteristics Analysis of “N-curve” and Static Noise Margin for Prediction of Yield of SRAM Cell Array

^○Tomoko Mizutani¹, Yoshiki Yamamoto², Hideki Makiyama², Hirofumi Shinohara², Toshiaki Iwamatsu², Hidekazu Oda², Shiro Kamohara², Nobuyuki Sugii², Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, LEAP²)

10:15 AM - 10:30 AM

[19a-F12-6] FinFET-based pseudo-spin-MOSFET and its nonvolatile SRAM application

^○Yusuke Shuto^1,2, Shuu'ichirou Yamamoto^1,2, Satoshi Sugahara¹ (ISEL, Tokyo Inst. Tech.¹, KAST²)

Break 10:30〜10:45 （10:30 AM - 10:45 AM）

10:45 AM - 11:00 AM

[19a-F12-7] Self-Image Potential in Electron Transport under Nano-Device Structures

^○（B）Yosuke Tsuchiya¹, Katsuhisa Yoshida¹, Nobuyuki Sano¹ (Inst. Appl. Phys, Univ. of Tsukuba¹)

11:00 AM - 11:15 AM

△ [19a-F12-8] Carrier Mobility and Discrete Impurity Scattering in Nanowire Structures

^○（B）Yuki Tanoue¹, Nobuyuki Sano¹ (Inst. Appl. Phys., Univ. of Tsukuba¹)

11:15 AM - 11:30 AM

△ [19a-F12-9] Impacts of Cross-sectional Shape on Phonon-limited Electron Mobility in Rectangular Ge Nanowires

^○Hajime Tanaka¹, Seigo Mori¹, Naoya Morioka¹, Jun Suda¹, Tsunenobu Kimoto¹ (Kyoto Univ.¹)

11:30 AM - 11:45 AM

[19a-F12-10] On the drain bias dependencies of tunnel FETs

^○Koichi Fukuda¹, Takahiro Mori¹, Wataru Mizubayashi¹, Akito Tanabe¹, Meishoku Masahara¹, Tetsuji Yasuda¹, Shinji Migita¹, Hiroyuki Ota¹, Yukinori Morita¹ (AIST GNC¹)

11:45 AM - 12:00 PM

[19a-F12-11] Performance enhancement of tunnel FinFET by synthetic electric field effect

^○Yukinori Morita¹, Takahiro Mori¹, Shinji Migita¹, Wataru Mizubayashi¹, Akihito Tanabe¹, koichi Fukuda¹, Kazuhiko Endo¹, Takashi Matsukawa¹, Shin-ichi O'uchi¹, Y.X. Liu¹, Meishoku Masahara¹, Hiroyuki Ota¹ (GNC-AIST¹)

12:00 PM - 12:15 PM

[19a-F12-12] Feasibility Study of ON Current Enhancement of TFETs by Utilizing Isovalent Traps

^○Takahiro Mori¹, Yukinori Morita¹, Noriyuki Miyata¹, Shinji Migita¹, Meishoku Masahara¹, Tetsuji Yasuda¹, Hiroyuki Ota¹ (GNC-AIST¹)

12:15 PM - 12:30 PM

[19a-F12-13] Compensation doping effect of TFET using InAs nanowire/Si heterojunction

^○Katsuhiro Tomioka^1,2, Fumiya Ishizaka¹, Eiji Nakai¹, Takashi Fukui¹ (GS-IST and RCIQE¹, JST-PRESTO²)

Oral presentation

[19p-F12-1~20] 13.4 Devices/Integration Technologies

Wed. Mar 19, 2014 1:30 PM - 6:45 PM F12 (F408)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

+Add all to schedule

Lunch 12:30〜13:30 （12:30 PM - 1:30 PM）

1:30 PM - 1:45 PM

[19p-F12-1] Experimental Study on 2D-Si Layers for Future Several-nm CMOS (Ⅵ)

^○Yuusuke Nagata¹, Yuuta Nakahara¹, Yuuya Suzuki¹, Kengo Saita¹, Yuuki Nagamine¹, Takashi Aoki¹, Toshiyuki Sammejima², Tomohisa Mizuno¹ (Kanagawa Univ¹, Tokyo Univ. Agri. Tech²)

1:45 PM - 2:00 PM

[19p-F12-2] Experimental Study on 2D-Si layers for Future Several-CMOS(Ⅶ)

^○Yuta Nakahara¹, Yusuke Nagata¹, Yuya Suzuki¹, Takashi Aoki¹, Toshiyuki Sameshima², Tomohisa Mizuno¹ (Kanagawa Univ.¹, Tokyo Univ. Agri. Tech.²)

2:00 PM - 2:15 PM

[19p-F12-3] Potential Performance of SOI MOSFET Single-Photon Detector

^○Yuki Nakagami¹, Dedy Septono Catur Putranto^1,2, Hiroaki Satoh¹, Atsushi Ono¹, Purnomo Sidi Priambodo², Djoko Hartanto², Hiroshi Inokawa¹ (Shizuoka Univ.¹, Univ. of Indonesia²)

2:15 PM - 2:30 PM

[19p-F12-4] A high-speed single-electron pump using a single trap level

^○Gento Yamahata¹, Katsuhiko Nishiguchi¹, Akira Fujiwara¹ (NTT Basic Research Labs.¹)

2:30 PM - 2:45 PM

[19p-F12-5] Peak Position Control of Coulomb Oscillations in Silicon Single-Electron Transistors with Floating Gate Operating at Room Temperature

^○Yuma Tanahashi^1,2, Ryota Suzuki¹, Takuya Saraya¹, Toshiro Hiramoto¹ (Univ of Tokyo¹, Chuo Univ²)

2:45 PM - 3:00 PM

[19p-F12-6] Fabrication and characterization of Si quantum dots using SF6 dry etching technique

^○Yi Lu¹, Tetsuo Kodera^1,2,3, Kousuke Horibe¹, Shunri Oda¹ (QNERC, Tokyo Tech.¹, NanoQuine, Univ. of Tokyo², JST-PRESTO³)

3:00 PM - 3:15 PM

[19p-F12-7] Magnetic field dependence of p-Channel Si Double Quantum Dot by Hole Transport

^○Ko Yamada¹, Tetsuo Kodera^1,2,3, Tomohiro Kambara¹, Kosuke Horibe¹, Yukio Kawano¹, Shunri Oda¹ (QNERC, Tokyo Tech¹, NanoQuine, Univ. of Tokyo², JST-PRESTO³)

3:15 PM - 3:30 PM

△ [19p-F12-8] Observation of Pauli Spin Blockade in Si/SiGe Double Quantum Dots

^○Jun Kamioka¹, Kenta Takeda², Toshiaki Obata², Tetsuo Kodera^1,3,4, Seigo Tarucha^2,3,5, Shunri Oda¹ (QNERC, Tokyo Tech.¹, Tokyo Univ.², NanoQuine, Tokyo Univ.³, JST-PRESTO⁴, RIKEN⁵)

3:30 PM - 3:45 PM

△ [19p-F12-9] Analysis of electron spin resonance in Si quantum dots with local magnetic field induced by integrated anisotropic ferromagnets

^○Tomohiro Kambara¹, Tetsuo Kodera^1,2,3, Shunri Oda¹ (QNERC¹, NanoQuine, Univ. of Tokyo², JST-PRESTO³)

3:45 PM - 4:00 PM

[19p-F12-10] Charge frustration of triangular triple quantum dot with charge sensor

^○Raisei Mizokuchi¹, Tetsuo Kodera^1,2,3, Kosuke Horibe¹, Shunri Oda¹ (QNERC, Tokyo Tech¹, NanoQuine, the Univ. of Tokyo², PRESTO-JST³)

4:00 PM - 4:15 PM

[19p-F12-11] Control of coupling capacitance of double quantum dot Si-SET by using multiple-gates

^○Takafumi Uchida¹, Isamu Yoshioka¹, Hikaru Sato¹, Masashi Arita¹, Akira Fujiwara², Yasuo Takahashi¹ (IST. Hokkaido Univ.¹, NTT Basic Research Labs.²)

4:15 PM - 4:30 PM

[19p-F12-12] Creation of high functionality of three-terminal Nanodot Array device

^○Isamu Yoshioka¹, Takafumi Uchida¹, Hikaru Satou¹, Masashi Arita¹, Akira Fujiwara², Yasuo Takahashi¹ (IST. Hokkaido Univ.¹, NTT Basic Research Labs.²)

Break 16:30〜16:45 （4:30 PM - 4:45 PM）

4:45 PM - 5:00 PM

[19p-F12-13] High performance strained GeOI nMOSFETs with in-situ doped epitaxial SiGe stressors

^○Yuuichi Kamimuta¹, Yoshihiko Moriyama¹, Eiko Mieda¹, Tatsuro Maeda¹, Jevasuwan Wipakorn¹, Yuichi Kurashima², Hideki Takagi², Minoru Oda¹, Toshifumi Irisawa¹, Keiji Ikeda¹, Etsuo Kurosawa¹, Tsutomu Tezuka¹ (GNC-AIST¹, AIST²)

5:00 PM - 5:15 PM

▲ [19p-F12-14] Ultrathin body Germanium-on-insulator (GeOI) MOSFETs fabricated by transfer of epitaxial Ge films on III-V substrates

^○Xiao Yu^1,2, Rui Zhang^1,2, Jian Kang^1,2, Tatsuro Maeda³, Taro Itatani³, Takenori Osada⁴, Masahiko Hata⁴, Mitsuru Takenaka^1,2, Shinichi Takagi^1,2 (Univ. of Tokyo¹, JST-CREST², AIST³, Sumitomo Chem.⁴)

5:15 PM - 5:30 PM

▲ [19p-F12-15] High Mobility Strained-Ge pMOSFETs with 0.7-nm Ultrathin EOT using Plasma Post Oxidation HfO₂/Al₂O₃/GeO_x Gate Stacks

^○（P）Rui Zhang^1,2,4, Winston Chern³, Xiao Yu^1,2, Mitsuru Takenaka^1,2, Hoyt Judy³, Shinichi Takagi^1,2 (Univ. Tokyo¹, JST CREST², MIT³, Zhejiang Univ.⁴)

5:30 PM - 5:45 PM

[19p-F12-16] Demonstration of poly-Ge short channel p- and n-MOSFETs fabricated by flash lamp annealing

^○Koji Usuda¹, Yoshiki Kamata¹, Yuuichi Kamimuta¹, Takahiro Mori¹, Masahiro Koike¹, Tsutomu Tezuka¹ (AIST-GNC¹)

5:45 PM - 6:00 PM

[19p-F12-17] Poly-Ge Normally-off Junctionless p-&n-MISFETs with Single Metal Gate

^○Yoshiki Kamata¹, Masahiro Koike¹, Yuuichi Kamimuta¹, Etsuo Kurosawa¹, Tsutomu Tezuka¹ (GNC AIST¹)

6:00 PM - 6:15 PM

[19p-F12-18] Ultra-thin GeSn pMOSFETs on Si (111) by solid phase epitaxy

^○Tatsuro Maeda¹, Wipakorn Jevasuwan¹, Hiroyuki Hattori¹, Noriyuki Uchida¹, Shu Miura², Masatoshi Tanaka², Jean Locquet³, Ruben Lieten^3,4 (AIST¹, YNU², KU Leuven³, IMEC⁴)

6:15 PM - 6:30 PM

[19p-F12-19] Examination of electrical properties of metal/GaSb junctions using metal-GaSb alloys

^○Koichi Nishi^1,2, SangHyeon Kim^1,2, Masafumi Yokoyama¹, Haruki Yokoyama³, Mitsuru Takenaka^1,2, Shinichi Takagi^1,2 (Tokyo Univ.¹, JST CREST², NTT Photonics Lab.³)

6:30 PM - 6:45 PM

[19p-F12-20] GaSb-OI p-MOSFETs on Si fabricated by direct wafer bonding technology

^○Masafumi Yokoyama¹, Koichi Nishi^1,2, Haruki Yokoyama³, Mitsuru Takenaka^1,2, Shinichi Takagi^1,2 (Univ. of Tokyo¹, JST CREST², NTT Photonics Labs.³)

Oral presentation

[20a-F12-1~13] 13.4 Devices/Integration Technologies

Thu. Mar 20, 2014 9:00 AM - 12:30 PM F12 (F408)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

+Add all to schedule

9:00 AM - 9:15 AM

[20a-F12-1] Fabrication and Characterization of the charge trapping type FinFET flash memories with a high-k Al2O3 blocking layer

^○Yongxun Liu¹, Toshihide Nabatame², Takashi Matsukawa¹, Kazuhiko Endo¹, Shinichi Ouchi¹, Jyunichi Tsukada¹, Hiromi Yamauchi¹, Yuki Ishikawa¹, Wataru Mizubayashi¹, Yukinori Morita¹, Shinji Migita¹, Hiroyuki Ota¹, Toshihiro Chikiyow², Meishoku Masahara¹ (AIST¹, NIMS²)

9:15 AM - 9:30 AM

[20a-F12-2] An Optimum Asymmetric Coding Strategy to Improve Program-Disturb Error in 2X, 3X and 4Xnm NAND Flash Memories

^○（M1）Masafumi Doi¹, Shuhei Tanakamaru^1,2, Ken Takeuchi¹ (Chuo Univ.¹, Univ. of Tokyo²)

9:30 AM - 9:45 AM

[20a-F12-3] Controller Technologies for Highly Reliable TLC NAND Flash Memory

^○（B）Tsukasa Tokutomi¹, Shuhei Tanakamaru^1,2, Ken Takeuchi¹ (Chuo Univ.¹, Univ. of Tokyo.²)

9:45 AM - 10:00 AM

[20a-F12-4] Switching characteristics of Cu-MoO_x-Al₂O₃ReRAM

^○Takahiro Hiroi¹, Akitoshi Nakane¹, Takashi Fujimoto¹, Masashi Arita¹, Yasuo Takahashi¹, Hideyuki Ando², Takashi Morie² (Graduate School of IST, Hokkaido Univ.¹, Graduate School of LSSE, Kyushu Institute of Technology²)

10:00 AM - 10:15 AM

[20a-F12-5] Study on resistance switching of WOx film prepared on an Al electrode

^○Akitoshi Nakane¹, Takahiro Hiroi¹, Masashi Arita¹, Yasuo Takahashi¹, Hideyuki Ando², Takashi Morie² (Graduate of IST,Hokkaido Univ.¹, Kyushu Inst.Technol²)

10:15 AM - 10:30 AM

[20a-F12-6] In-situ TEM observation of WO_x ReRAMs with Cu Top Electrodes

^○Akihito Takahashi¹, Yuuki Ohno¹, Akitoshi Nakane¹, Masaki Kudo¹, Kouichi Hamada¹, Masashi Arita¹, Yasuo Takahashi¹ (Graduate School of IST, Hokkaido Univ.¹)

10:30 AM - 10:45 AM

[20a-F12-7] Filament formation during repeatedly resistive switching of Cu / MoOx ReRAMs

^○Masaki Kudo¹, Yuuki Ohno¹, Takahiro Hiroi¹, Takashi Fujimoto², Kouichi Hamada¹, Masashi Arita¹, Yasuo Takahashi¹ (Graduate School of IST, Hokkaido Univ.¹, Faculty of Eng. , Hokkaido Univ.²)

Break 10:45〜11:00 （10:45 AM - 11:00 AM）

11:00 AM - 11:15 AM

▲ [20a-F12-8] Verify-Program Method Investigation and Optimization on 50nm AlxOy ReRAM Array

^○Sheyang Ning^1,2, Ogura Tomoko Iwasaki¹, Ken Takeuchi¹ (Chuo Univ.¹, Univ. of Tokyo²)

11:15 AM - 11:30 AM

▲ [20a-F12-9] Investigation of AlxOy ReRAM Cell Resistance Switch Characteristic

^○Sheyang Ning^1,2, Ogura Tomoko Iwasaki¹, Ken Takeuchi¹ (Chuo Univ.¹, Univ. of Tokyo²)

11:30 AM - 11:45 AM

[20a-F12-10] Controller Technologies for Highly Reliable and High Performance ReRAM

^○（B）Hiroki Yamazawa¹, Shuhei Tanakamaru^1,2, Ken Takeuchi¹ (Chuo Univ.¹, Univ. of Tokyo²)

11:45 AM - 12:00 PM

△ [20a-F12-11] Three-Terminal One-Time Programmable Switch Using CMOS Transistor

^○Koichiro Zaitsu¹, Kosuke Tatsumura¹, Masato Oda¹, Shinichi Yasuda¹ (Toshiba Corp.¹)

12:00 PM - 12:15 PM

[20a-F12-12] Switching Operation of Bidirectional TaO Diode-selected Complementary Atom Switches (DCAS) for Area-efficient Crossbar Switch

^○Koichiro Okamoto¹, Munehiro Tada¹, Naoki Banno¹, Toshitsugu Sakamoto¹, Noriyuki Iguchi¹, Tatsuhiko Nohisa¹, Hiromitsu Hada¹ (LEAP¹)

12:15 PM - 12:30 PM

[20a-F12-13] Bias-stress Reliability of OFF-state Complementary Atom Switch

^○Naoki Banno¹, Munehiro Tada¹, Toshitsugu Sakamoto¹, Makoto Miyamura¹, Koichiro Okamoto¹, Noriyuki Iguchi¹, Tatsuhiko Nohisa¹, Hiromitsu Hada¹ (LEAP¹)

Oral presentation

[20p-F12-1~6] 13.4 Devices/Integration Technologies

Thu. Mar 20, 2014 1:30 PM - 3:00 PM F12 (F408)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

+Add all to schedule

Lunch 12:30〜13:30 （12:30 PM - 1:30 PM）

1:30 PM - 1:45 PM

[20p-F12-1] EDMR Study of RTS after NBT Stress

^○Yoshiki Yonamoto¹ (Hitachi, Ltd., Yokohama Laboratory¹)

1:45 PM - 2:00 PM

[20p-F12-2] Incident-energy dependency of secondary cosmic-ray neutron-induced soft errors

^○（P）Shin-ichiro Abe^1,2, Yukinobu Watanabe¹ (Kyushu Univ.¹, JSPS Research Fellow²)

2:00 PM - 2:15 PM

△ [20p-F12-3] Development of Time-Domain Charge Pumping Technique

^○Tokinobu Watanabe¹, Masahiro Hori¹, Toshiaki Tsuchiya², Yukinori Ono¹ (Univ. of Toyama¹, Shimane Univ.²)

2:15 PM - 2:30 PM

[20p-F12-4] Surface Orientation Impacts on Random Telegraph Noise Related Carriers time constants and Current Fluctuations in nMOSFETs

^○jiezhi chen¹, Izumi Hirano¹, Yuichiro Mitani¹ (Toshiba R&D Center¹)

2:30 PM - 2:45 PM

[20p-F12-5] Drain Current Dependence of Statistical Distribution of Random Telegraph Noise (RTN) in Scaled MOSFETs

^○（M2）Hitoshi Ohno¹, Tomoko Mizutani¹, Toshiro Hiramoto¹ (IIS¹)

2:45 PM - 3:00 PM

▲ [20p-F12-6] |Vth| Shifts and Their Variability Behaviors in pFETs by High Voltage ON-State and OFF-State Stress

^○Nurul Ezaila Alias¹, Anil Kumar¹, Takuya Saraya¹, Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹)

Sessions

13. Semiconductors A (Silicon) » 13.4 Devices/Integration Technologies

[18p-PA12-1~10] 13.4 Devices/Integration Technologies

△ [18p-PA12-5] Ultra-thin body Ge-on insulator nMOSFETs by Ge condensation and Sb-diffused source/drain

[19a-F12-1~13] 13.4 Devices/Integration Technologies

△ [19a-F12-2] Evaluation of Self-Heating Effects in Nanoscale Bulk and Ultra-Thin BOX SOI MOSFETs Using Four-Terminal Gate Resistance Technique

△ [19a-F12-8] Carrier Mobility and Discrete Impurity Scattering in Nanowire Structures

△ [19a-F12-9] Impacts of Cross-sectional Shape on Phonon-limited Electron Mobility in Rectangular Ge Nanowires

[19p-F12-1~20] 13.4 Devices/Integration Technologies

△ [19p-F12-8] Observation of Pauli Spin Blockade in Si/SiGe Double Quantum Dots

△ [19p-F12-9] Analysis of electron spin resonance in Si quantum dots with local magnetic field induced by integrated anisotropic ferromagnets

▲ [19p-F12-14] Ultrathin body Germanium-on-insulator (GeOI) MOSFETs fabricated by transfer of epitaxial Ge films on III-V substrates

▲ [19p-F12-15] High Mobility Strained-Ge pMOSFETs with 0.7-nm Ultrathin EOT using Plasma Post Oxidation HfO2/Al2O3/GeOx Gate Stacks

[20a-F12-1~13] 13.4 Devices/Integration Technologies

▲ [20a-F12-8] Verify-Program Method Investigation and Optimization on 50nm AlxOy ReRAM Array

▲ [20a-F12-9] Investigation of AlxOy ReRAM Cell Resistance Switch Characteristic

△ [20a-F12-11] Three-Terminal One-Time Programmable Switch Using CMOS Transistor

[20p-F12-1~6] 13.4 Devices/Integration Technologies

△ [20p-F12-3] Development of Time-Domain Charge Pumping Technique

▲ [20p-F12-6] |Vth| Shifts and Their Variability Behaviors in pFETs by High Voltage ON-State and OFF-State Stress

▲ [19p-F12-15] High Mobility Strained-Ge pMOSFETs with 0.7-nm Ultrathin EOT using Plasma Post Oxidation HfO₂/Al₂O₃/GeO_x Gate Stacks