Symposium

[13p-4C-1~9] What is the last knob of Ge-CMOS?

Sun. Sep 13, 2015 1:15 PM - 5:00 PM 4C (432)

座長:右田真司(産総研),最上徹(PETRA)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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1:15 PM - 1:30 PM

[13p-4C-1] Introduction - Be positive about germanium!

〇Akira Toriumi¹ (1.Univ. Tokyo)

1:30 PM - 2:00 PM

▲ [13p-4C-2] High Mobility Ge CMOS Devices with Ultrathin EOT Gate Stacks Fabricated by Plasma Post Oxidation

〇Rui Zhang¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.The Univ. of Tokyo)

2:00 PM - 2:15 PM

[13p-4C-3] Wet Cleaning and Surface Preparation for SiGe and Ge

〇Hiroaki Takahashi¹, Masayuki Wada¹, Yukifumi Yoshida², Farid Sebaai³, Frank Holsteyns³, Paul Mertens³, Masanobu Sato¹, Hajime Shirakawa¹ (1.SCREEN, 2.SCREEN SPE Germany, 3.imec)

2:15 PM - 2:45 PM

▲ [13p-4C-4] How to secure both sufficient passivation and long term reliability in Ge gate stack
-The key is to keep a proper network structure of oxides-

〇Cimang Lu¹, Tomonori Nishimura¹, Akira Toriumi¹ (1.The Univ. of Tokyo)

Break （2:45 PM - 3:00 PM）

3:00 PM - 3:15 PM

[13p-4C-5] Characterization of thin Ge layer on GeOI substrate fabricated
by Epitaxial Lift-Off (ELO) technique

〇Yuuichi Kurashima¹, Hideki Takagi¹, Hiroyuki Ishii¹, Hiroyuki Hattori¹, Wen-Hsin Chang¹, Tatsuro Maeda¹ (1.AIST)

3:15 PM - 3:30 PM

▲ [13p-4C-6] Impact of back interface passivation on electrical properties of ultrathin-body Germanium-on-insulator (GeOI) MOSFETs

〇(D)Xiao YU^1,2, Jian Kang^1,2, Rui Zhang¹, Wei.-Li Cai^1,2, Mitsuru Takenaka^1,2, Shinichi Takagi^1,2 (1.the Univ. of Tokyo, 2.JST-CREST)

3:30 PM - 4:00 PM

[13p-4C-7] Carrier Activation Enhancement and Ultra-low Contact Resistance for Ge CMOS

〇Hidenori Miyoshi¹, Tetsuji Ueno¹, Koji Akiyama¹, Yoshihiro Hirota¹, Takanobu Kaitsuka¹ (1.Tokyo Electron Ltd.)

4:00 PM - 4:30 PM

[13p-4C-8] Trends in Developing Ge-CMOS Integration Technologies

〇Tsutomu Tezuka^1,2, Keiji Ikeda^1,2, Toshifumi Irisawa², Yoshiki Kamata^1,2, Koji Usuda^1,2, Yuuichi Kamimuta^1,2, Yoshihiko Moriyama^1,2, Masahiro Koike^1,2, Minoru Oda^1,2, Mizuki Ono^1,2 (1.Toshiba R&D Center, 2.GNC-AIST)

4:30 PM - 5:00 PM

▲ [13p-4C-9] Germanium for advanced CMOS transistors: Status and Trends

〇Jerome Mitard¹, Liesbeth Witters¹, Hiro Arimura¹, Yuichiro Sasaki¹, Alexei Milenin¹, Roger Loo¹, Andriy Hikavyy¹, Geert Eneman¹, Pieter Lagrain¹, Hans Mertens¹, Sonja Sioncke¹, Christa Vrancken¹, Hugo Bender¹, Naoto Horiguchi¹, Anda Mocuta¹, Nadine Collaert¹, Aaron Thean¹ (1.Imec, Kapeldreef 75, B-3001 Leuven, Belgium)

Sessions

Symposium » What is the last knob of Ge-CMOS?

[13p-4C-1~9] What is the last knob of Ge-CMOS?

[13p-4C-1] Introduction - Be positive about germanium!

▲ [13p-4C-2] High Mobility Ge CMOS Devices with Ultrathin EOT Gate Stacks Fabricated by Plasma Post Oxidation

[13p-4C-3] Wet Cleaning and Surface Preparation for SiGe and Ge

▲ [13p-4C-4] How to secure both sufficient passivation and long term reliability in Ge gate stack
-The key is to keep a proper network structure of oxides-

[13p-4C-5] Characterization of thin Ge layer on GeOI substrate fabricated
by Epitaxial Lift-Off (ELO) technique

▲ [13p-4C-6] Impact of back interface passivation on electrical properties of ultrathin-body Germanium-on-insulator (GeOI) MOSFETs

[13p-4C-7] Carrier Activation Enhancement and Ultra-low Contact Resistance for Ge CMOS

[13p-4C-8] Trends in Developing Ge-CMOS Integration Technologies

▲ [13p-4C-9] Germanium for advanced CMOS transistors: Status and Trends

Authentication

Sessions

Symposium » What is the last knob of Ge-CMOS?

[13p-4C-1~9] What is the last knob of Ge-CMOS?

[13p-4C-1] Introduction - Be positive about germanium!

▲ [13p-4C-2] High Mobility Ge CMOS Devices with Ultrathin EOT Gate Stacks Fabricated by Plasma Post Oxidation

[13p-4C-3] Wet Cleaning and Surface Preparation for SiGe and Ge

▲ [13p-4C-4] How to secure both sufficient passivation and long term reliability in Ge gate stack-The key is to keep a proper network structure of oxides-

[13p-4C-5] Characterization of thin Ge layer on GeOI substrate fabricatedby Epitaxial Lift-Off (ELO) technique

▲ [13p-4C-6] Impact of back interface passivation on electrical properties of ultrathin-body Germanium-on-insulator (GeOI) MOSFETs

[13p-4C-7] Carrier Activation Enhancement and Ultra-low Contact Resistance for Ge CMOS

[13p-4C-8] Trends in Developing Ge-CMOS Integration Technologies

▲ [13p-4C-9] Germanium for advanced CMOS transistors: Status and Trends

Authentication

▲ [13p-4C-4] How to secure both sufficient passivation and long term reliability in Ge gate stack
-The key is to keep a proper network structure of oxides-

[13p-4C-5] Characterization of thin Ge layer on GeOI substrate fabricated
by Epitaxial Lift-Off (ELO) technique