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13 Semiconductors » 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

[16a-E206-1~13] 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

Thu. Mar 16, 2017 9:00 AM - 12:15 PM E206 (E206)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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9:00 AM - 9:15 AM

[16a-E206-1] Cleanroom-Free Environment Control System for Minimal PLAD(Ⅱ)

〇Takashi Yajima^1,2, Masaharu Yasui^1,2, Sommawan Khumpuang^1,2, Hitoshi Maekawa^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL)

9:15 AM - 9:30 AM

[16a-E206-2] Study of uniformity on thermal oxide formed on a wafer by a minimal laser heating furnace(2)

〇kazushige sato¹, Takashi Chiba^1,3, Masao Terada^1,3, Shinichi Ikeda^1,2, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.Minimal Fab Development Association, 2.AIST, 3.Sakaguchi E.H VOC Corp)

9:30 AM - 9:45 AM

[16a-E206-3] Silicon Nitride Film Formations Using the New Magnetically-Confined ECR Plasma Source for Minimal Fab System

〇Tetsuya Goto¹, Kei-ichiro Sato², Yuki Yabuta³, Shigetoshi Sugawa¹, Shiro Hara^4,5 (1.Tohoku Univ., 2.Kotec, 3.Seinan Industries, 4.AIST, 5.MINIMAL)

9:45 AM - 10:00 AM

[16a-E206-4] Minimal CVD Process with Minimum Materials Consumption

〇Hitoshi Habuka¹, Miya Matsuo¹, Ayami Yamada¹, Ning Li¹, Takanori Mikahara^2,3, Shin-ichi Ikeda^2,3, Yuuki Ishida^2,3, Shiro Hara^2,3 (1.Yokohama Nat. Univ., 2.MINIMAL, 3.AIST)

10:00 AM - 10:15 AM

[16a-E206-5] Factor of the thickness distribution on the Minimal Si-CVD equipment

〇Shinichi Ikeda^1,2, Yuuki Ishida^1,2, Takanori Mikahara^1,2, Noriko Miura², Takahiro Ito³, Hitoshi Habuka⁴, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL, 3.ORIENTAL MOTOR, 4.YOKOHAMA National Univ.)

10:15 AM - 10:30 AM

[16a-E206-6] Development of Water Plasma Ashing Technology for Minimal Fabrication System

〇Takeshi Aizawa¹, Takeshi Yamada¹, Mitsunori Nogawa¹, Yasuhiro Onishi¹, Noriko Miura^1,3, Tatsuo Ishijima², Takuya Kitano², Hiroaki Suzuki², Arufa Shiota², Sommawan Khumpuang^3,4, Shiro Hara^3,4 (1.Yonekura MFG., 2.Kanazawa Univ., 3.Minimal, 4.AIST)

10:30 AM - 10:45 AM

[16a-E206-7] Through silicon via etching with high-speed gas-switching Bosch process using minimal ICP deep trench etcher (II)

〇Hiroyuki Tanaka^1,2, Hisato Ogiso^1,2, Shizuka Nakano^1,2, Yoshiyuki Nozawa^2,3, Toshihiro Hayami^2,3, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL, 3.SPPT)

10:45 AM - 11:00 AM

[16a-E206-8] Fabrication of Microneedle Array using Minimal Fab

〇Sommawan Khumpuang^1,2, Norio Umeyama^1,2, Hiroyuki Tanaka^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL)

11:00 AM - 11:15 AM

[16a-E206-9] Fabrication of SOI Optical Waveguide using Minimal Fab

〇JUNYA KURUMIDA^1,2, Hiroyuki Tanaka^1,2, Norio Umeyama^1,2, Khumpuang Sommawan^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL)

11:15 AM - 11:30 AM

[16a-E206-10] CMOSFET Fabrication by Minimal Spin-on Dopant Process using Plasma Enhanced CVD TEOS as Thermal diffusion mask(Ⅱ)

〇Kazuhiro Koga^1,2, Fumito Imura^1,2, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL)

11:30 AM - 11:45 AM

[16a-E206-11] Minimal SOI-CMOS Fabrication Using Soild Source Diffusion by Spin on Dopants

〇Yongxun Liu¹, Kazuhiro Koga^1,2, Sommawan Khumpuang^1,2, Masayoshi Ngao¹, Takashi Matsukawa¹, Shiro Hara^1,2 (1.AIST, 2.MINIMAL)

11:45 AM - 12:00 PM

[16a-E206-12] Fan-Out type RDL package fabrication using hybrid process of minimal package process and conventional metal PVD

〇Masanori Iwata¹, Toru Mannami¹, Nobuyoshi Yamauchi¹, Kenji Miyake¹, Fumito Imura², Sommawan Khumpuang², Shiro Hara² (1.PMT, 2.AIST)

12:00 PM - 12:15 PM

[16a-E206-13] Electrical Characteristics of Half-Inch Sized Package Fabricated by Minimal Fab

〇Fumito Imura^1,2, Takuya Koga², Michihiro Inoue¹, Arami Saruwatari^1,2, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.Minimal Fab)

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